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PERFORMANCE FEATURES ADSP-21060 Core Processor (. . . 4) 480 MFLOPS Peak, 320 MFLOPS Sustained 25 ns Instruction Rate, Single-Cycle Instruction Execution-Each of Four Processors 16 Mbit Shared SRAM (Internal to SHARCs) 4 Gigawords Addressable Off-Module Memory Sixteen 40 Mbyte/s Link Ports (Four per SHARC) Eight 40 Mbit/s Independent Serial Ports (Two from Each SHARC) 5 V and 3.3 V Operation 32-Bit Single Precision and 40-Bit Extended Precision IEEE Floating Point Data Formats, or 32-Bit Fixed Point Data Format IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation PACKAGING FEATURES 452-Lead Ceramic Ball Grid Array (CBGA) 1.85" (47 mm) Body Size 0.200" Max Height 0.050" Ball Pitch 29 Grams (typical) JC = 0.36 C/W
TIMEXP LINK 1 LINK 2 CS
Quad-SHARC(R) DSP Multiprocessor Family AD14160/AD14160L
FUNCTIONAL BLOCK DIAGRAM
LINK 3 LINK 4 TIMEXP LINK 1 LINK 2 LINK 3 FLAG3-0 LINK 4 CS FLAG3-0 IRQ2-0 IRQ2-0 TCK, TMS, TRST
TCK, TMS, TRST
EBOOT, LBOOT, BMS EMU CLKIN
EBOOT, LBOOT, BMS EMU CLKIN
ID2-0 CPA SPORT 1 SPORT 0 TDI
LINK 0 LINK 5 TDO
LINK 0 LINK 5 TDI
SHARC_A
SHARC_B
ID2-0 CPA SPORT 1 SPORT 0
RESET
RESET
AD14160/ AD14160L
SHARC BUS (ADDR31-0, DATA47-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR6-1, RPBA, DMAR1.2, DMAG1.2)
EBOOT, LBOOT, BMS
EMU CLKIN
EBOOT, LBOOT, BMS EMU CLKIN
RESET
TCK, TMS, TRST
RESET
TCK, TMS, TRST
FLAG3-0
LINK 1
LINK 2
LINK 3
LINK 4
LINK 1
LINK 2
LINK 3
LINK 4
IRQ2-0
GENERAL DESCRIPTION
The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid Array (CBGA) puts the power of the first generation AD14060 (CQFP) DSP multiprocessor into a very high density ball grid array package; now with additional link and serial I/O pinned out, beyond that from the CQFP package. The core of the multiprocessor is the ADSP-21060 DSP microcomputer. The AD14x60 modules have the highest performance--density and lowest cost-- performance ratios of any in their class. They are ideal for applications requiring higher levels of performance and/or functionality per unit area. The AD14160/AD14160L takes advantage of the built-in multiprocessing features of the ADSP-21060 to achieve 480 peak MFLOPS with a single chip type, in a single package. The onchip SRAM of the DSPs provides 16 Mbits of on-module shared SRAM. The complete shared bus (48 data, 32 address) is also brought off-module for interfacing with expansion memory or other peripherals.
The ADSP-21060 link ports are interconnected to provide direct communication among the four SHARCs as well as high speed off-module access. Internally, links connect the SHARC in a ring. Externally, each SHARC has a total of 160 Mbytes/s link port bandwidth. Multiprocessor performance is enhanced with embedded power and ground planes, matched impedance interconnect, and optimized signal routing lengths and separation. The fully tested and ready-to-insert multiprocessor also significantly reduces board space.
SHARC is a registered trademark of Analog Devices, Inc.
s s s s
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
IRQ2-0
CS
CS
LINK 5 TDI
LINK 5 TDO
FLAG3-0
TIMEXP
TIMEXP
ID2-0 CPA SPORT 1 SPORT 0 TDO
SHARC_D
LINK 0
LINK 0
SHARC_C
ID2-0 CPA SPORT 1 SPORT 0
TDI
TDO
AD14160/AD14160L
DETAILED DESCRIPTION Architectural Features ADSP-21060 Core
The AD14160/AD14160L is based on the powerful ADSP-21060 (SHARC) DSP chip. The ADSP-21060 SHARC combines a high performance floating-point DSP core with integrated, onchip system features including a 4 Mbit SRAM memory, host processor interface, DMA controller, serial ports, and both link port and parallel bus connectivity for glueless DSP multiprocessing, (see Figure 1). It is fabricated in a high speed, low power CMOS process, and has a 25 ns instruction cycle time. The arithmetic/ logic unit (ALU), multiplier and shifter all perform singlecycle instructions, and the three units are arranged in parallel, maximizing computational throughput. The SHARC features an enhanced Harvard architecture in which the data memory (DM) bus transfers data, and the program memory (PM) bus transfers both instructions and data. There is also an on-chip instruction cache which selectively caches only those instructions whose fetches conflict with the PM bus data accesses. This combines with the separate program and data memory buses to enable three-bus operation for fetching an instruction and two operands, all in a single cycle. The SHARC also contains a general purpose data register file, which
CORE PROCESSOR
TIMER INSTRUCTION CACHE
32 x 48-BIT ADDR ADDR
is a 10-port, 32-register (16 primary, 16 secondary) file. Each SHARC's core also implements two data address generators (DAGs), implementing circular data buffers in hardware. The DAGs contain sufficient registers to allow the creation of up to 32 circular buffers. The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21060 can conditionally execute a multiply, an add, a subtract, and a branch, all in a single instruction. The SHARCs contain 4 Mbits of on-chip SRAM each, organized as two blocks of 2 Mbits, which can be configured for different combinations of code and data storage. The memory can be configured as a maximum of 128K words of 32-bit data, 256K words of 16-bit data, 80K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 4 megabits. A 16-bit floating-point storage format is supported which effectively doubles the amount of data that may be stored on chip. Conversion between the 32-bit floating point and 16bit floating point formats is done in a single instruction. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor or DMA controller. The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle.
DUAL-PORTED SRAM
BLOCK 0 BLOCK 1
TWO INDEPENDENT DUAL-PORTED BLOCKS PROCESSOR PORT
DATA DATA
JTAG
TEST AND EMULATION
7
I/O PORT
DATA DATA ADDR ADDR
DAG1
8 x 4 x 32
DAG2
8 x 4 x 24
PROGRAM SEQUENCER 24 32 IOD 48 IOA 17
PM ADDRESS BUS DM ADDRESS BUS
EXTERNAL PORT
ADDR BUS MUX MULTIPROCESSOR INTERFACE 32
PM DATA BUS 48
BUS CONNECT (PX)
DM DATA BUS 40/32
DATA BUS MUX HOST PORT
48
DATA REGISTER FILE MULTIPLIER
16 x 40-BIT
IOP REGISTERS (MEMORY MAPPED) BARREL SHIFTER ALU CONTROL, STATUS, AND DATA BUFFERS
DMA CONTROLLER SERIAL PORTS (2) LINK PORTS (6)
4 6 6 36
I/O PROCESSOR
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14160/AD14160L)
-2-
REV. A
AD14160/AD14160L
0x0000 0000 0x0040 0000 BANK 0 DRAM (OPTIONAL)
INTERNAL MEMORY SPACE (INDIVIDUAL SHARCs)
IOP REGISTERS 0x0002 0000 NORMAL WORD ADDRESSING 0x0004 0000 SHORT WORD ADDRESSING 0x0008 0000 INTERNAL MEMORY SPACE OF SHARC_A ID=001 0x0010 0000 INTERNAL MEMORY SPACE OF SHARC_B ID=010 0x0018 0000 INTERNAL MEMORY SPACE OF SHARC_C ID=011 0x0020 0000 INTERNAL MEMORY SPACE OF SHARC_D ID=100 0x0028 0000 INTERNAL MEMORY SPACE OF ADSP-2106x WITH ID=101 0x0030 0000 INTERNAL MEMORY SPACE OF ADSP-2106x WITH ID=110 0x0038 0000 BROADCAST WRITE TO ALL ADSP-2106xs 0x003F FFFF NORMAL WORD ADDRESSING: 32-BIT DATA WORDS 48-BIT INSTRUCTION WORDS SHORT WORD ADDRESSING: 16-BIT DATA WORDS NONBANKED BANK SIZE IS SELECTED BY MSIZE BIT FIELD OF SYSCON REGISTER. BANK 2 MS2 BANK 1 MS1 MS0
INTERNAL TO AD14160x
MULTIPROCESSOR MEMORY SPACE
EXTERNAL MEMORY SPACE
BANK 3 MS3
EXTERNAL TO AD14160x
0xFFFF FFFF
Figure 2. AD14160/AD14160L Memory Map
SYSTEM EXPANSION
1X CLOCK
CLKIN RESET
SHARC_A
LINKS 1, 2, 3, & 4; IRQ2-0; FLAG 3-0; TIMEXP, SPORT1 CPA ID2-0
ADDR31-0 LINKS 1, 2, 3, & 4; DATA47-0 IRQ2-0; FLAG 3-0; RD TIMEXP, WR SPORT1 ACK CPA ID2-0 MS3-0 PAGE SBTS SW ADRCLK CS HBR HBG REDY BR1-6 RPBA
SHARC_B
BOOTSELECT A BOOTSELECT BCD DMAR1,2 DMAG1,2
AD14160/ AD14160L
(QUAD PROCESSOR CLUSTER)
SHARC_D
LINKS 1, 2, 3, & 4; IRQ2-0; FLAG 3-0; TIMEXP, SPORT1 CPA ID2-0
SHARC_C
LINKS 1, 2, 3, & 4; IRQ2-0; FLAG 3-0; TIMEXP, SPORT1 CPA ID2-0
SPORT0 SPORT1 JTAG
Figure 3. Complete Shared Memory Multiprocessing System
REV. A
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AD14160/AD14160L
Shared Memory Multiprocessing
The AD14160/AD14160L takes advantage of the powerful multiprocessing features built into the SHARC. The SHARCs are connected to maximize the performance of this cluster-of-four architecture, and still allow for off-module expansion. The AD14160/AD14160L in itself is a complete shared memory multiprocessing system, as shown in Figure 3. The unified address space of the SHARCs allows direct interprocessor accesses of each SHARCs' internal memory. In other words, each SHARC can directly access the internal memory and IOP registers of each of the other SHARCs by simply reading or writing to the appropriate address in multi-processor memory space (see Figure 2)--this is called a direct read or direct write. Bus arbitration is accomplished with the on-SHARC arbitration logic. Each SHARC has a unique ID, and drives the Bus-Request (BR) line corresponding to its ID, while monitoring all others. BR1-BR4 are used within the AD14160/AD14160L, while BR5 and BR6 can be used for expansion. All bus requests (BR1-BR6) are included in the module I/O. Two different priority schemes, fixed and rotating, are available to resolve competing bus requests. The RPBA pin selects which scheme is used: when RPBA is high, rotating priority bus arbitration is selected, and when RPBA is low, fixed priority is selected.
Table I. Rotating Priority Arbitration Example
Cycle 1 2 3 4 5 ID1 M 4 4 5 BR 1 BR Hardware Processor IDs ID2 ID3 ID4 ID5 ID6 1 5 BR 5 BR M 2 2 BR M-BR M 1 3 3 1 1 2 4 4 2 2 3 5 5 Initial Priority Assignments 3 3 4 BR M Final Priority Assignments
The bus master can communicate with slave SHARCs by writing messages to their internal IOP registers. The MSRG0- MSRG7 registers are general-purpose registers that can be used for convenient message passing, semaphores and resource sharing between the SHARCs. For message passing, the master communicates with a slave by writing and/or reading any of the eight message registers on the slave. For vector interrupts, the master can issue a vector interrupt to a slave by writing the address of an interrupt service routine to the slave's VIRPT register. This causes an immediate high priority interrupt on the slave which, when serviced, will cause it to branch to the specified service routine.
Off-Module Memory and Peripherals Interface
The AD14160/AD14160L's external port provides the interface to off-module memory and peripherals (see Figure 5). This port consists of the complete external port bus of the SHARC, bused together in common among the four SHARCs. The 4-gigaword off-module address space is included in the AD14160/AD14160L's unified address space. Addressing of external memory devices is facilitated by each SHARC internally decoding the high order address lines to generate memory bank select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The AD14160/ AD14160L also supports programmable memory wait states and external memory acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold and disable time requirements.
Link Port I/O
NOTES 1-5 = Assigned Priority. M = Bus Mastership (in that cycle). BR = Requesting Bus Mastership with BRx.
Each individual SHARC features six 4-bit link ports that facilitate SHARC-to-SHARC communication and external I/O interfacing. Each link port can be configured for either 1x or 2x operation, allowing each to transfer either 4 or 8 bits per cycle. The link ports can operate independently and simultaneously, with a maximum bandwidth of 40 MBytes/s each, or a total of 240 MBytes/s per SHARC. The AD14160/AD14160L provides additional link port I/O beyond that of the AD14060. Internally, two links from each SHARC form a ring connection among the four. The remaining four link ports from each SHARC are brought out independently from each SHARC. A maximum of 640 MBytes/s link port bandwidth is then available off of the AD14160/AD14160L. The link port connections are detailed in Figure 4.
Bus mastership is passed from one SHARC to another during a bus transition cycle. A bus transition cycle only occurs when the current bus master deasserts its BR line and one of the slave SHARCs asserts its BR line. The bus master can therefore retain bus mastership by keeping its BR line asserted. When the bus master deasserts its BR line, and no other BR line is asserted, then the master will not lose any bus cycles. When more than one SHARC asserts its BR line, the SHARC with the highest priority request becomes bus master on the following cycle. Each SHARC observes all of the BR lines, and therefore tracks when a bus transition cycle has occurred, and which processor has become the new bus master. Master processor changeover incurs only one cycle of overhead. An example bus transition sequence is shown in Table I. Bus locking is possible, allowing indivisible read-modify-write sequences for semaphores. In either the fixed or rotating priority scheme, it is also possible to limit the number of cycles the master can control the bus. The AD14160/AD14160L also provides the option of using the Core Priority Access (CPA) mode of the SHARC. Using the CPA signal allows external bus accesses by the core processor of a slave SHARC to take priority over ongoing DMA transfers. Also, each SHARC can broadcast write to all other SHARCs simultaneously, allowing the implementation of reflective semaphores. -4-
1 2 3 4 0 0 1 2 3 4 0 0 5 5
1 2
SHARC_A
SHARC_B
3 4
1 2
SHARC_D
5 5
SHARC_C
3 4
Figure 4. Link Port Connections
REV. A
AD14160/AD14160L
AD14160/ AD14160L
1x CLOCK RESET CLKIN RESET RPBA 3 ID ADDR31-0 DATA47-0 RD WR ACK MS3-0 BMS PAGE SBTS SW ADRCLK CS HBR HBG REDY SERIALS LINKS DISCRETES CPA BR2-6 BR1 ADDR 5 DATA ADDR DATA OE WE ACK CS CS ADDR DATA GLOBAL MEMORY AND PERIPHERALS (OPTIONAL)
CONTROL
BOOT EPROM (OPTIONAL)
HOST PROCESSOR INTERFACE (OPTIONAL)
ADSP-2106x #5
CLKIN (OPTIONAL) ADDR31-0 DATA47-0
RESET RPBA 3 ID CONTROL
CPA BR1, 2, 3, 4, 6 BR5
5
ADSP-2106x #6
(OPTIONAL) CLKIN RESET RPBA 3 ID ADDR31-0 DATA47-0
CONTROL
CPA BR1-5 BR6
5
Figure 5. Optional System Interconnections
REV. A
-5-
AD14160/AD14160L
Link port 4, the boot link port, is brought off independently from each SHARC. Individual booting is then allowed, or chained link port booting is possible as described under "Link Port Booting." Link port data is packed into 32-bit or 48-bit words, and can be directly read by the SHARC core processor or DMA-transferred to on-SHARC memory. Each link port has its own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as either transmit or receive.
Serial Ports
to become bus master and boot itself. Only the BMS pin of SHARC_A is connected to the chip select of the EPROM. When SHARC_A has finished booting, it can boot the remaining ADSP-21060s by writing to their external port DMA buffer 0 (EPB0) via multiprocessor memory space. All ADSP-21060s Boot in Turn From a Single EPROM. The BMS signals from each ADSP-21060 may be wire-ORed together to drive the chip select pin of the EPROM. Each ADSP-21060 can boot in turn, according to its priority. When the last one has finished booting, it must inform the others (which may be in the idle state) that program execution can begin.
Multiprocessor Link Port Booting
The SHARC serial ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. Each SHARC has two serial ports. All eight of the AD14160/AD14160L serial ports are brought off-module. The serial ports can operate at the full clock rate of the module, providing each with a maximum data rate of 40 Mbit/s. Independent transmit and receive functions provide more flexible communications. Serial port data can be automatically transferred to and from on-SHARC memory via DMA, and each of the serial ports offers time division multiplexed (TDM) multichannel mode. The serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. They offer selectable synchronization and transmit modes as well as optional -law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated.
Program Booting
Booting can also be accomplished from a single source through the link ports. Link Buffer 4 must always be used for booting. To simultaneously boot all of the ADSP-21060s, a parallel common connection is available through Link Port 4 on each of the processors. Or, using the daisy chain connection that exists between the processors' link ports, each ADSP-21060 can boot the next one in turn. In this case, the Link Assignment Register (LAR) must be programmed to configure the internal link ports with Link Buffer 4.
Multiprocessor Booting From External Memory
If external memory contains a program after reset, then SHARC_A should be set up for no boot mode; it will begin executing from address 0x0040 0004 in external memory. When booting has completed, the other ADSP-21060s may be booted by SHARC_A if they are set up for host booting, or they can begin executing out of external memory if they are set up for no boot mode. Multiprocessor bus arbitration will allow this booting to occur in an orderly manner.
Host Processor Interface
The AD14160/AD14160L supports automatic downloading of programs following power-up or a software reset. The SHARC offers four options for program booting: 1) from an 8-bit EPROM; 2) from a host processor; 3) through the link ports; and 4) no-boot. In no-boot mode, the SHARC starts executing instructions from address 0x0040 0004 in external memory. The boot mode is selected by the state of the following signals: BMS, EBOOT, and LBOOT. On the AD14160/AD14160L, SHARC_A's boot mode is separately controlled, while SHARCs B, C, and D are controlled as a group. With this flexibility, the AD14160/AD14160L can be configured to boot in any of the following methods.
Multiprocessor Host Booting
The AD14160/AD14160L's host interface allows for easy connection to standard microprocessor buses, both 16-bit and 32bit, with little additional hardware required. Asynchronous transfers at speeds up to the full clock rate of the module are supported. The host interface is accessed through the AD14160/ AD14160L external port and is memory-mapped into the unified address space. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor requests the AD14160/AD14160L's external bus with the host bus request (HBR), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the internal memory of the SHARCs, and can access the DMA channel setup and mailbox registers. Vector interrupt support is provided for efficient execution of host commands.
Direct Memory Access (DMA) Controller
To boot multiple ADSP-21060 processors from a host, each ADSP-21060 must have its EBOOT, LBOOT and BMS pins configured for host booting: EBOOT = 0, LBOOT = 0, and BMS = 1. After system power-up, each ADSP-21060 will be in the idle state and the BRx bus request lines will be deasserted. The host must assert the HBR input and boot each ADSP-21060 by asserting its CS pin and downloading instructions.
Multiprocessor EPROM Booting
The SHARCs on-chip DMA control logic allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to each SHARCs processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between SHARC internal memory and either external memory, external peripherals, or a host processor. DMA transfers can also occur between the SHARC's internal memory and its serial ports or link ports. DMA transfers between external memory and external peripheral devices are another option. External bus packing to 16-, 32- or 48-bit words is performed during DMA transfers. -6- REV. A
There are two methods of booting the multiprocessor system from an EPROM. SHARC_A Is Booted, Which Then Boots the Others. The EBOOT pin on the SHARC_A must be set high for EPROM booting. All other ADSP-21060s should be configured for host booting (EBOOT = 0, LBOOT = 0, and BMS = 1), which leaves them in the idle state at start-up and allows SHARC_A
AD14160/AD14160L
Ten channels of DMA are available on the SHARCs--two via the link ports, four via the serial ports, and four via the processor's external port (for either host processor, other SHARCs, memory, or I/O transfers). Four additional link port DMA channels are shared with serial port 1 and the external port. Programs can be downloaded to the SHARCs using DMA transfers. Asynchronous off-module peripherals can control two DMA channels using DMA Request/Grant lines (DMAR1-2, DMAG1-2). Other DMA features include interrupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers.
Development Tools
EZ-ICE provides full-speed emulation, allowing inspection and modification of memory, registers and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. Further details and ordering information are available in the ADSP-21000 Family Hardware & Software Development Tools data sheet (ADDS-2100xx-TOOLS). This data sheet can be requested from any Analog Devices sales office or distributor, or from the Literature Center. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC PC plug-in cards, multiprocessor SHARC VME boards, and daughter card modules with multiple SHARCs and additional memory. These modules are based on the SHARCPACTM module specification. Third party software tools include an Ada compiler, DSP libraries, operating systems and block diagram design tools.
Other Package Details
The AD14160/AD14160L is supported with a complete set of software and hardware development tools, including an EZ-LAB(R) In-Circuit Emulator, and development software. Analog Devices' ADSP-21000 Family Development Software includes an easy to use Assembler based on an algebraic syntax, an Assembly Library/Librarian, a Linker, an Instruction-Level Simulator, an ANSI C optimizing Compiler, the CBugTM C Source-Level Debugger, and a C Runtime Library including DSP and mathematical functions. The Optimizing Compiler includes Numerical C extensions based on the work of the ANSI Numerical C Extensions Group. Numerical C provides extensions to the C language for array selection, vector math operations, complex data types, circular pointers and variably dimensioned arrays. The ADSP-21000 Family Development Software is available for both the PC and Sun platforms. The SHARC EZ-KIT combines the ADSP-21000 Family Development Software for the PC and the EZ-LAB Development Board in one package. The ADSP-2106x EZ-ICE(R) Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x processor to monitor and control the target board processor during emulation. The
The AD14160/AD14160L contains 14 on-module 0.1 microfarad bypass capacitors. It is recommended that in the target system at least four additional capacitors, of 0.018 microfarad value, be placed around the module--one near each of the four corners. The top surface, lid, of the AD14160/AD14160L is electrically connected to GND.
Additional Information
This data sheet provides a general overview of the AD14160/ AD14160L architecture and functionality. For detailed information on the ADSP-2106x SHARC and the ADSP-21000 Family core architecture and instruction set, refer to the ADSP-2106x SHARC User's Manual.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc. CBug and SHARCPAC are trademarks of Analog Devices, Inc.
REV. A
-7-
AD14160/AD14160L
PIN FUNCTION DESCRIPTIONS
AD14160/AD14160L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to VDD or GND, except for ADDR31-0, DATA47-0, FLAG2-0, SW, and inputs that have internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx, Pin ADDR31-0 Type I/O/T Function
TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS and TDI)--these pins can be left floating. These pins have a logiclevel hold circuit that prevents the input from floating internally. A = Asynchronous O = Output (A/D) = Active Drive G = Ground P = Power Supply (O/D) = Open Drain I = Input S = Synchronous T = Three-State (when SBTS is asserted, or when the AD14160/ AD14160L is a bus slave)
DATA47-0
I/O/T
External Bus Address. (Common to all SHARCs) The AD14160/AD14160L outputs addresses for external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes on the internal memory or IOP registers of slave ADSP-2106xs. The AD14160/ AD14160L inputs addresses when a host processor or multiprocessing bus master is reading or writing the internal memory or IOP registers of internal ADSP-21060s. External Bus Data. (Common to all SHARCs) The AD14160/AD14160L inputs and outputs data and instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47-16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 478 of the bus. 16-bit short word data is transferred over bits 31-16 of the bus. In PROM boot mode, 8-bit data is transferred over bits 23-16. Pull-up resistors on unused DATA pins are not necessary. Memory Select Lines. (Common to all SHARCs) These lines are asserted (low) as chip selects for the corresponding banks of external memory. Memory bank size must be defined in the individual ADSP21060's system control registers (SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring the MS3-0 lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system, the MS3-0 lines are output by the bus master. Memory Read Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14160/ AD14160L reads from external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices (including other ADSP-2106xs) must assert RD to read from the AD14160/ AD14160L's internal memory. In a multiprocessing system, RD is output by the bus master and is input by all other ADSP-2106xs. Memory Write Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14160/ AD14160L writes to external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices (including other ADSP-2106xs) must assert WR to write to the AD14160/ AD14160L's internal memory. In a multiprocessing system WR is output by the bus master and is input by all other ADSP-2106xs. DRAM Page Boundary. (Common to all SHARCs) The AD14160/AD14160L asserts this pin to signal that an external DRAM page boundary has been crossed. DRAM page size must be defined in the individual ADSP-21060's memory control register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system, PAGE is output by the bus master. Clock Output Reference. (Common to all SHARCs) In a multiprocessing system, ADRCLK is output by the bus master. Synchronous Write Select. (Common to all SHARCs) This signal is used to interface the AD14160/ AD14160L to synchronous memory devices (including other ADSP-2106xs). The AD14160/AD14160L asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same time as the address output. A host processor using synchronous writes must assert this pin when writing to the AD14160/AD14160L. Memory Acknowledge. (Common to all SHARCs) External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The AD14160/AD14160L deasserts ACK, as an output, to add wait states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-2106x deasserts the bus master's ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level it was last driven to. -8- REV. A
MS3-0
O/T
RD
I/O/T
WR
I/O/T
PAGE
O/T
ADRCLK SW
O/T I/O/T
ACK
I/O/S
AD14160/AD14160L
Pin SBTS Type I/S Function Suspend Bus Three-State. (Common to all SHARCs) External devices can assert SBTS (low) to place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. If the AD14160/AD14160L attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host processor/AD14160/AD14160L deadlock, or used with a DRAM controller. Host Bus Request. (Common to all SHARCs) Must be asserted by a host processor to request control of the AD14160/AD14160L's external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address, data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests (BR6-1) in a multiprocessing system. Host Bus Grant. (Common to all SHARCs) Acknowledges an HBR bus request, indicating that the host processor may take control of the external bus. HBG is asserted (held low) by the AD14160/ AD14160L until HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others. Chip Select. Asserted by host processor to select SHARC_A. Chip Select. Asserted by host processor to select SHARC_B. Chip Select. Asserted by host processor to select SHARC_C. Chip Select. Asserted by host processor to select SHARC_D. Host Bus Acknowledge. (Common to all SHARCs) The AD14160/AD14160L deasserts REDY (low) to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP21060s to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted. Multiprocessing Bus Requests. (Common to all SHARCs) Used by multiprocessing ADSP-2106xs to arbitrate for bus mastership. An ADSP-2106x only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be pulled high; BR4-1 must not be pulled high or low because they are outputs. Multiprocessing ID. (Individual ID2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D.) Determines which multiprocessing bus request (BR1-BR6) is used by individual ADSP-2106x's. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 is reserved for single processor systems. These lines are a system configuration selection, which should be hardwired or only changed at reset. Rotating Priority Bus Arbitration Select. (Common to all SHARCs) When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x. Core Priority Access. (y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is required. The CPA pin of each internal ADSP-21060 is brought out individually. The CPA pin has an internal 5 k pull-up resistor. If core access priority is not required in a system, the CPA pin should be left unconnected. Data Transmit (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). DT pin has a 50 k internal pull-up resistor. Data Receive (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). DR pin has a 50 k internal pull-up resistor. Transmit Clock (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). TCLK pin has a 50 k internal pull-up resistor. Receive Clock (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). RCLK pin has a 50 k internal pull-up resistor. Transmit Frame Sync (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). Receive Frame Sync (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
HBR
I/A
HBG
I/O
CSA CSB CSC CSD REDY (O/D)
I/A I/A I/A I/A O
BR6-1
I/O/S
IDy2-0
I
RPBA
I/S
CPAy (O/D)
I/O
DTy0 DRy0 TCLKy0 RCLKy0 TFSy0 RFSy0
O/T I I/O I/O I/O I/O
REV. A
-9-
AD14160/AD14160L
Pin DTy1 DRy1 TCLKy1 RCLKy1 TFSy1 RFSy1 FLAGy3-0 Type O/T I I/O I/O I/O I/O I/O/A Function Data Transmit (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin has a 50 k internal pull-up resistor. Data Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin has a 50 k internal pull-up resistor. Transmit Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) TCLK pin has a 50 k internal pull-up resistor. Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK pin has a 50 k internal pull-up resistor. Transmit Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Receive Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Flag Pins. (Individual FLAG3-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. Interrupt Request Lines. (Individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) May be either edge-triggered or level-sensitive. DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D. DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D. DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D. DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D. Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 2, 3, 4)1. Each LyxCLK pin has a 50 k internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the ADSP-20160. Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 2, 3, 4)1. Each LyxDAT pin has a 50 k internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the ADSP-21060. Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 2, 3, 4)1. Each LyxACK pin has a 50 k internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the ADSP-21060. EPROM Boot Select. (SHARC_A) When EBOOTA is high, SHARC_A is configured for booting from an 8-bit EPROM. When EBOOTA is low, the LBOOTA and BMSA inputs determine booting mode for SHARC_A. See the following table. This signal is a system configuration selection which should be hardwired. Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is low, SHARC_A is configured for host processor booting or no booting. See the following table. This signal is a system configuration selection which should be hardwired. Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTA = 1, LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will occur and that SHARC_A will begin executing instructions from external memory. See the following table. This input is a system configuration selection which should be hardwired. EPROM Boot Select. (Common to SHARC_B, SHARC_C, SHARC_D) When EBOOTBCD is high, SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the LBOOTBCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following table. This signal is a system configuration selection which should be hardwired. LINK Boot. (Common to SHARC_B, SHARC_C, SHARC_D) When LBOOTBCD is high, SHARC_B, C, D are configured for link port booting. When LBOOTBCD is low, SHARC_B, C, D are configured for host processor booting or no booting. See the following table. This signal is a system configuration selection which should be hardwired.
IRQy2-0 DMAR1 DMAR2 DMAG1 DMAG2 LyxCLK
I/A I/A I/A O/T O/T I/O
LyxDAT3-0
I/O
LyxACK
I/O
EBOOTA
I
LBOOTA
I
BMSA
I/O/T2
EBOOTBCD
I
LBOOTBCD
I
-10-
REV. A
AD14160/AD14160L
Pin BMSBCD Type I/O/T
2
Function Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTBCD = 1, LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will occur and that SHARC_B, C, D will begin executing instructions from external memory. See table below. This input is a system configuration selection which should be hardwired. EBOOT 1 0 0 0 0 1 LBOOT 0 0 1 0 1 1 BMS Output 1 (Input) 1 (Input) 0 (Input) 0 (Input) x (Input) Booting Mode EPROM (Connect BMS to EPROM chip select) Host Processor Link Port No Booting. Processor executes from external memory. Reserved Reserved
TIMEXPy CLKIN
O I
Timer Expired. (Individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero. Clock In. (Common to all SHARCs) External clock input to the AD14160/AD14160L. The instruction cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified frequency. Module Reset. (Common to all SHARCs) Resets the AD14160/AD14160L to a known state. This input must be asserted (low) at power-up. Test Clock (JTAG). (Common to all SHARCs) Provides an asynchronous clock for JTAG boundary scan. Test Mode Select (JTAG). (Common to all SHARCs) Used to control the test state machine. TMS has a 20 k internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A. TDI has a 20 k internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D. Test Reset (JTAG). (Common to all SHARCs) Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the AD14160/AD14160L. TRST has a 20 k internal pull-up resistor. Emulation Status. (Common to all SHARCs) Must be connected to the ADSP-2106x EZ-ICE target board connector only. Power Supply. Nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices (50 pins). Power Supply Return. (64 pins).
RESET TCK TMS TDI TDO TRST
I/A I I/S I/S O I/A
EMU (O/D) VDD GND
O P G
NOTES 1 LINK PORTS 0 and 5 are connected internally as described earlier in Link Port I/O. 2 Three-statable only in EPROM boot mode (when BMS is an output).
REV. A
-11-
AD14160/AD14160L
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x to monitor and control the target board processor during emulation. The EZ-ICE probe requires that the AD14160/AD14160L's CLKIN (optional), TMS, TCK, TRST, TDI, TDO, EMU and GND signals be made accessible on the target system via a 14-pin connector (a pin strip header) such as that shown in Figure 6. The EZICE probe plugs directly onto this connector for chip-on-board emulation. You must add this connector to your target board design if you intend to use the ADSP-2106x EZ-ICE. The length of the traces between the connector and the AD14160/ AD14160L's JTAG pins should be as short as possible.
1 GND 3 KEY (NO PIN) 5 BTMS 7 BTCK 9 BTRST 11 BTDI 13 GND TOP VIEW 14 TDO 9 12 TDI 10 TRST 8 TCK 6 TMS 4 CLKIN (OPTIONAL) 2 EMU
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location; Pin 3 must be removed from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 x 0.1 inches. Pin strip headers are available from vendors such as 3M, McKenzie and Samtec. The BTMS, BTCK, BTRST and BTDI signals are provided so that the test access port can also be used for board-level testing. When the connector is not being used for emulation, place jumpers between the Bxxx pins and the xxx pins as shown in Figure 6. If you are not going to use the test access port for board testing, tie BTRST to GND and tie or pull up BTCK to VDD. The TRST pin must be asserted after power-up (through BTRST on the connector) or held low for proper operation of the AD14160/AD14160L. None of the Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE probe. The JTAG signals are terminated on the EZ-ICE probe as follows: Signal TMS TCK TRST TDI TDO CLKIN EMU Termination Driven through 22 Resistor (16 mA/3.2 mA Driver) Driven at 10 MHz through 22 Resistor (16 mA/ 3.2 mA Driver) Driven by Open-Drain Driver* (Pulled Up by On-Chip 20 k Resistor) Driven by 16 mA/3.2 mA Driver One TTL Load, No Termination One TTL Load, No Termination (Optional Signal) 4.7 k Pull-Up Resistor, One TTL Load (Open-Drain Output from ADSP-2106x)
*TRST is driven low until the EZ-ICE probe is turned on by the EZ-ICE software (after the invocation command).
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE Emulator (Jumpers in Place)
Figure 7 shows JTAG scan path connections for the multiprocessor system.
SHARC_A
TDI EZ-ICE JTAG CONNECTOR OTHER JTAG CONTROLLER TCK TMS EMU TRST TDO CLKIN OPTIONAL TDI EMU TMS TCK TDO TRST
SHARC_B
TDI EMU TMS TCK TDO TRST
SHARC_C
TDI EMU TMS TCK TDO TRST
SHARC_D
TDI EMU TMS TCK TDO TRST
JTAG DEVICE (OPTIONAL) TDI TMS TCK TDO TRST
ADSP-2106x #n TDI EMU TMS TCK TDO TRST
Figure 7. JTAG Scan Path Connections for the AD14160/AD14160L
-12-
REV. A
AD14160/AD14160L
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when directed to perform operations such as starting, stopping and single-stepping multiple ADSP-2106xs in a synchronous manner. If you do not need these operations to occur synchronously on the multiple processors, simply tie Pin 4 of the EZ-ICE header to ground. If synchronous multiprocessor operations are needed and CLKIN is connected, clock skew between the AD14160/ AD14160L and the CLKIN pin on the EZ-ICE header must be minimal. If the skew is too large, synchronous operations may be off by one cycle between processors. For synchronous multiprocessor operation TCK, TMS, CLKIN and EMU should be
TDI TDO TDI
treated as critical signals in terms of skew, and should be laid out as short as possible on your board. If TCK, TMS and CLKIN are driving a large number of ADSP-2106xs (more than eight) in your system, then treat them as a "clock tree" using multiple drivers to minimize skew. (See Figure 8 JTAG Clock Tree and Clock Distribution in the "High Frequency Design Considerations" section of the ADSP-2106x User's Manual). If synchronous multiprocessor operations are not needed (i.e., CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not critical signals in terms of skew.
TDO
TDI
TDO
5k
*
TDI
TDO
TDI
TDO
TDI
TDO
TDI EMU TCK TMS TRST TDO CLKIN
5k
*
EMU
SYSTEM CLKIN
*OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
Figure 8. JTAG Clocktree for Multiple ADSP-2106x Systems
REV. A
-13-
AD14160/AD14160L-SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter VDD TCASE Supply Voltage (5 V) Supply Voltage (3.3 V) Case Operating Temperature B Grade Min Max 4.75 3.15 -40 5.25 3.6 +100 K Grade Min Max 4.75 3.15 0 5.25 3.6 +85 Units V V C
ELECTRICAL CHARACTERISTICS (5 V, 3.3 V SUPPLY)
Parameter VIH1 VIH2 VIL VOH VOL IIH IIHX4 IIL IILX4 IILP IILPX4 IOZH IOZHX4 IOZL IOZLX4 IOZHP IOZLC IOZLAR IOZLA IOZLS IDDIN IDDIDLE CIN High Level Input Voltage High Level Input Voltage2 Low Level Input Voltage1, 2 High Level Output Voltage3, 4 Low Level Output Voltage3, 4 High Level Input Current5, 6 High Level Input Current7, 8 Low Level Input Current5 Low Level Input Current7 Low Level Input Current6 Low Level Input Current8 Three-State Leakage Current9, 10, 11 Three-State Leakage Current12 Three-State Leakage Current9, 13 Three-State Leakage Current12 Three-State Leakage Current13 Three-State Leakage Current14 Three-State Leakage Current11 Three-State Leakage Current15 Three-State Leakage Current10 Supply Current (Internal)16 Supply Current (Idle)17 Input Capacitance18, 19
1
Case Test Temp Level Test Condition Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full +25C I I I I I I I I I I I I I I I I I I I I IV I V
5V Min Typ Max
3.3 V Min Typ Max VDD + 0.5 VDD + 0.5 0.8 0.4 10 40 10 40 150 600 10 40 10 40 350 1.5 4.2 350 150 2.2 760
Units V V V V V A A A A A A A A A A A mA mA A A A mA
@ VDD = max 2.0 @ VDD = max 2.2 @ VDD = min @ VDD = min, IOH = -2.0 mA4 4.1 @ VDD = min, IOL = 4.0 mA4 @ VDD = max, VIN = VDD max @ VDD = max, VIN = VDD max @ VDD = max, VIN = 0 V @ VDD = max, VIN = 0 V @ VDD = max, VIN = 0 V @ VDD = max, VIN = 0 V @ VDD = max, VIN = VDD max @ VDD = max, VIN = VDD max @ VDD = max, VIN = 0 V @ VDD = max, VIN = 0 V @ VDD = max, VIN = VDD max @ VDD = max, VIN = 0 V @ VDD = max, VIN = 0 V @ VDD = max, VIN = 2 V (3.3 V), 1.5 V (5 V) @ VDD = max, VIN = 0 V tCK = 25 ns, VDD = max VDD = max
VDD + 0.5 2.0 VDD + 0.5 2.2 0.8 2.4 0.4 10 40 10 40 150 600 10 40 10 40 350 1.5 4.2 350 150 3.4 800
1.4
1
15
15
pF
EXPLANATION OF TEST LEVELS Test Level I 100% Production Tested20. II 100% Production Tested at +25C, and Sample Tested at Specified Temperatures. III Sample Tested Only. IV Parameter is guaranteed by design and analysis, and characterization testing on discrete SHARCs. V Parameter is typical value only. VI All devices are 100% production tested at +25C; sample tested at temperature extremes.
NOTES 1 Applies to input and bidirectional pins: DATA 47-0, ADDR 31-0, RD, WR, SW, ACK, SBTS, IRQy2-0, FLAGy0-3, HBG, CSy, DMAR1, DMAR2, BR6-1, IDy0-2, RPBA, CPAy, TFSy0, TFSy1, RFSy0, RFSy1, LyxDAT 3-0, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS, TDI, TCK, HBR, DRy0, DRy1, TCLKy0, TCLKy1, RCLKy0, RCLKy1. 2 Applies to input pins: CLKIN, RESET, TRST. 3 Applies to output and bidirectional pins: DATA 47-0, ADDR31-0, MS3-0 RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0-3, TIMEXPy, HBG, REDY, DMAG1, DMAG2, BR6-1, CPAy, DTy0, DTy1, TCLKy0, TCLKy1, RCLKy0, RCLKy1, TFSy0, TFSy1, RFSy0, RFSy1 LyxDAT 3-0, LyxCLK, LyxACK, BMSA, BMSBCD, TDO, EMU. 4 See Output Drive Currents for typical drive current capabilities. 5 Applies to input pins: IRQy2-0, CSy, IDy0-2, EBOOTA, LBOOTA. 6 Applies to input pins with internal pull-ups: DRy0, DRy1, TDI. 7 Applies to bussed input pins: SBTS, HBR, DMAR1, DMAR2, RPBA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK. 8 Applies to bussed input pins with internal pull-ups: TRST, TMS. 9 Applies to three-statable pins: FLAGy0-3, BMSA, TDO. 10 Applies to three-statable pins with internal pull-ups: DTy0, TCLKy0, RCLKy0, DTy1, TCLKy1, RCLKy1. 11 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID 2-0 = 001 and another ADSP-2106x is not requesting bus mastership.) 12 Applies to bussed three-statable pins: DATA 47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, REDY, HBG, DMAG1, DMAG2, BMSBCD, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID 2-0 = 001 and another ADSP-2106x is not requesting bus mastership. HBG and EMU are not tested for leakage current.)
-14-
REV. A
AD14160/AD14160L
13 14
Applies to three-statable pins with internal pull-downs: LyxDAT3-0, LyxCLK, LyxACK. Applies to CPAy pin. 15 Applies to ACK pin when keeper latch enabled. 16 Applies to V DD pins. Conditions of operation: each processor executing radix-2 FFT butterfly with instruction in cache, one data operand fetched from each internal memory block, and one DMA transfer occurring from/to internal memory at t CK = 25 ns. 17 Applies to V DD pins. Idle denotes AD14160/AD14160L state during execution of IDLE instruction. 18 Applies to all signal pins. 19 Guaranteed but not tested. 20 Link and Serial Ports: All are 100% tested at die level prior to assembly. All are 100% ac tested at module level; Link-4 and Serial-0 are also dc tested at the module level. See Timing Specifications. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (5 V) . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Supply Voltage (3.3 V) . . . . . . . . . . . . . . . . -0.3 V to +4.6 V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output Voltage Swing . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Solder Ball Temperature (5 seconds) . . . . . . . . . . . . . +230C
*Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY The AD14160/AD14160L modules are ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur to devices subjected to high energy electrostatic discharges. The ADSP-21060 processors include proprietary ESD protection circuitry to dissipate high energy discharges. Per method 3015 of MIL-STD-883, the ADSP-21060 processors have been classified as a Class 2 device. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed.
WARNING!
ESD SENSITIVE DEVICE
TIMING SPECIFICATIONS
GENERAL NOTES
This data sheet represents production released specifications for the AD14160L (3.3 V), and the AD14160 (5 V). The ADSP21060 die components are 100% tested, and the assembled AD14160/AD14160L units are again extensively tested atspeed, and across-temperature. Parametric limits were established from the ADSP-21060 characterization followed by further design/analysis of the AD14160/AD14160L package characteristics. The specifications shown are based on a CLKIN frequency of 40 MHz (tCK = 25 ns). The DT derating allows specifications at other CLKIN frequencies (within the min-max range of the tCK specification; see "Clock Input" below). DT is the difference between the actual CLKIN period and a CLKIN period of 25 ns: DT = tCK - 25 ns Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times. Switching Characteristics specify how the processor changes its signals. You have no control over this timing--circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. (O/D) = Open Drain (A/D) = Active Drain
REV. A
-15-
AD14160/AD14160L
Parameter Clock Input Timing Requirements: CLKIN Period tCK tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V-2.0 V) 25 7 5 100 25 8.75 5 100 ns ns ns ns Min 40 MHz-5 V Max 40 MHz-3.3 V Min Max Units
3
tCK
3
CLKIN
tCKH
tCKL
Figure 9. Clock Input
Parameter Reset Timing Requirements: RESET Pulsewidth Low1 tWRST tSRST RESET Setup Before CLKIN High2
Min
40 MHz-5 V Max
40 MHz-3.3 V Min Max
Units
4tCK 14.5 + DT/2
tCK
4tCK 14.5 + DT/2
tCK
ns ns
NOTES 1 Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is low, assuming stable V DD and CLKIN (not including start-up time of external clock oscillator). 2 Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
tWRST
RESET
tSRST
Figure 10. Reset
Parameter Interrupts Timing Requirements: tSIR IRQ2-0 Setup Before CLKIN High1 tHIR IRQ2-0 Hold Before CLKIN High1 tIPW IRQ2-0 Pulsewidth2
NOTES 1 Only required for IRQx recognition in the following cycle. 2 Applies only if tSIR and tHIR requirements are not met.
Min
40 MHz-5 V Max
40 MHz-3.3 V Min Max
Units
18 + 3DT/4 12 + 3DT/4 2 + tCK
18 + 3DT/4 12 + 3DT/4 2 + tCK
ns ns ns
CLKIN
tSIR tHIR
IRQ2-0
tIPW
Figure 11. Interrupts
-16-
REV. A
AD14160/AD14160L
Parameter Timer Switching Characteristic: tDTEX CLKIN High to TIMEXP Min 40 MHz-5 V Max 40 MHz-3.3 V Min Max Units
15.5
15.5
ns
CLKIN
tDTEX
TIMEXP
tDTEX
Figure 12. Timer
Parameter Flags Timing Requirements: tSFI FLAG3-0IN Setup Before CLKIN High1 tHFI FLAG3-0IN Hold After CLKIN High1 tDWRFI FLAG3-0IN Delay After RD/WR Low1 tHFIWR FLAG3-0IN Hold After RD/WR Deasserted1 Switching Characteristics: FLAG3-0OUT Delay After CLKIN High tDFO tHFO FLAG3-0OUT Hold After CLKIN High tDFOE CLKIN High to FLAG3-0OUT Enable tDFOD CLKIN High to FLAG3-0OUT Disable
Min
40 MHz-5 V Max
40 MHz-3.3 V Min Max
Units
8 + 5DT/16 0 - 5DT/16 5 + 7DT/16 0.5
8 + 5DT/16 0 - 5DT/16 5 + 7DT/16 0.5
ns ns ns ns
16.5 4 3 14.5 4 3
16.5
14.5
ns ns ns ns
NOTE 1 Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
CLKIN
tDFOE tDFO
FLAG3-0OUT
tHFO
tDFO
tDFOD
FLAG OUTPUT
CLKIN
tSFI
FLAG3-0IN
tHFI
tDWRFI
RD, WR
tHFIWR
FLAG INPUT
Figure 13. Flags
REV. A
-17-
AD14160/AD14160L
Memory Read--Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the AD14160/ AD14160L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write--Bus Master below). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
40 MHz-5 V Parameter Timing Requirements: Address, Selects Delay to Data Valid 1, 2 tDAD RD Low to Data Valid1 tDRLD tHDA Data Hold from Address3 Data Hold from RD High3 tHDRH ACK Delay from Address 2, 4 tDAAK tDSAK ACK Delay from RD Low4 Switching Characteristics: tDRHA Address Hold After RD High Address to RD Low2 tDARL RD Pulsewidth tRW tRWR RD High to WR, RD, DMAGx Low tSADADC Address Setup Before ADRCLK High 2 Min Max 17 + DT + W 11 + 5DT/8 + W 1.5 3 13 + 7DT/8 + W 7 + DT/2 + W 1.5 3 Min
40 MHz-3.3 V Max 17 + DT + W 11 + 5DT/8 + W
Units ns ns ns ns ns ns
13 + 7DT/8 + W 7 + DT/2 + W
-1 + H 1 + 3DT/8 12.5 + 5DT/8 + W 7.5 + 3DT/8 + HI -0.5 + DT/4
-1 + H 1 + 3DT/8 12.5 + 5DT/8 + W 7.5 + 3DT/8 + HI -0.5 + DT/4
ns ns ns ns ns
W = (number of wait states specified in WAIT register) x tCK. HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0). NOTES Data Delay/Setup: User must meet t DAD or tDRLD or synchronous spec t SSDATI. For MSx, SW, BMS, the falling edge is referenced. 3 Data Hold: User must meet t HDA or tHDRH or synchronous spec t HDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times given capacitive and dc loads. 4 ACK Delay/Setup: User must meet t DSAK or tDAAK or synchronous specification t SACKC.
1 2
ADDRESS MSx, SW BMS
tDARL
RD
tRW
tDRHA
tHDA tDRLD tDAD
DATA
tHDRH
tDSAK tDAAK
ACK
tRWR
WR, DMAG
tSADADC
ADRCLK (OUT)
Figure 14. Memory Read--Bus Master
-18-
REV. A
AD14160/AD14160L
Memory Write--Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the AD14160/ AD14160L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write--Bus Master). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Parameter Timing Requirements: tDAAK ACK Delay from Address, Selects 1, 2 tDSAK ACK Delay from WR Low1 Switching Characteristics: tDAWH Address, Selects to WR Deasserted2 Address, Selects to WR Low2 tDAWL WR Pulsewidth tWW tDDWH Data Setup Before WR High Address Hold After WR Deasserted tDWHA Data Disable After WR Deasserted3 tDATRWH tWWR WR High to WR, RD, DMAGx Low Data Disable Before WR or RD Low tDDWR WR Low to Data Enabled tWDE tSADADC Address, Selects to ADRCLK High 2
Min
40 MHz-5 V Max 13 + 7DT/8 + W 7 + DT/2 + W
40 MHz-3.3 V Min Max 13 + 7DT/8 + W 7 + DT/2 + W Units ns ns
16 + 15DT/16 + W 2 + 3DT/8 12 + 9DT/16 + W 6 + DT/2 + W 0 + DT/16 + H 0.5 + DT/16 + H 7 + DT/16 + H 7.5 + 7DT/16 + H 4 + 3DT/8 + I -1.5 + DT/16 -0.5 + DT/4
16 + 15DT/16 + W 2 + 3DT/8 12 + 9DT/16 + W 6 + DT/2 + W 0 + DT/16 + H 0.5 + DT/16 + H 7 + DT/16 + H 7.5 + 7DT/16 + H 4 + 3DT/8 + I -1.5 + DT/16 -0.5 + DT/4
ns ns ns ns ns ns ns ns ns ns
W = (number of wait states specified in WAIT register) x tCK. H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0). I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0). NOTES ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification t SACKC. 2 For MSx, SW, BMS, the falling edge is referenced. 3 See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
1
ADDRESS MSx , SW BMS
tDAWH tDAWL
WR
tDWHA tWW
tWDE
tDDWH tDATRWH
tWWR tDDWR
DATA
tDSAK tDAAK
ACK
RD , DMAG
tSADADC
ADRCLK (OUT)
Figure 15. Memory Write--Bus Master
REV. A
-19-
AD14160/AD14160L
Synchronous Read/Write--Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN--relative timing or for accessing a slave ADSP-2106x (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes (see Memory Read--Bus Master and Memory Write--Bus Master).
When accessing a slave ADSP-2106x, these switching characteristics must meet the slave's timing requirements for synchronous read/writes (see Synchronous Read/Write--Bus Slave). The slave ADSP-2106x must also meet these (bus master) timing requirements for data and acknowledge setup and hold times.
Parameter Timing Requirements: tSSDATI Data Setup Before CLKIN Data Hold After CLKIN tHSDATI ACK Delay After Address, tDAAK MSx, SW, BMS1, 2 ACK Setup Before CLKIN2 tSACKC ACK Hold After CLKIN tHACKC Switching Characteristics: Address, MSx, BMS, SW Delay tDADRO After CLKIN1 Address, MSx, BMS, SW Hold tHADRO After CLKIN tDPGC PAGE Delay After CLKIN RD High Delay After CLKIN tDRDO WR High Delay After CLKIN tDWRO tDRWL RD/WR Low Delay After CLKIN Data Delay After CLKIN tSDDATO Data Disable After CLKIN 3 tDATTR tDADCCK ADRCLK Delay After CLKIN ADRCLK Period tADRCK ADRCLK Width High tADRCKH tADRCKL ADRCLK Width Low
Min
40 MHz-5 V Max
Min
40 MHz-3.3 V Max
Units ns ns
3.5 + DT/8 3.5 - DT/8 13 + 7 DT/8 + W 7 + DT/4 -1 - DT/4
3.5 + DT/8 3.5 - DT/8 13 + 7 DT/8 + W 7 + DT/4 -1 - DT/4
ns ns ns
8 - DT/8 -1 - DT/8 9 + DT/8 -2 - DT/8 -3 - 3DT/16 8 + DT/4 0 - DT/8 4 + DT/8 tCK (tCK/2 - 2) (tCK/2 - 2) -1 - DT/8 9 + DT/8 -2 - DT/8 -3 - 3DT/16 8 + DT/4 0 - DT/8 4 + DT/8 tCK (tCK/2 - 2) (tCK/2 - 2)
8 - DT/8
ns ns ns ns ns ns ns ns ns ns ns ns
16.5 + DT/8 5 - DT/8 5 - 3DT/16 13.5 + DT/4 20 + 5DT/16 8 - DT/8 10.5 + DT/8
16.5 + DT/8 5 - DT/8 5 - 3DT/16 13.5 + DT/4 20 + 5DT/16 8 - DT/8 10.5 + DT/8
W = (number of Wait states specified in WAIT register) x tCK. NOTES For MSx, SW, BMS, the falling edge is referenced. 2 ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification t SACKC. 3 See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
1
-20-
REV. A
AD14160/AD14160L
CLKIN
tADRCK tDADCCK
ADRCLK
tADRCKH
tADRCKL
tHADRO tDADRO
ADDRESS SW
tDAAK
tDPGC
PAGE
tHACKC tSACKC
ACK (IN)
READ CYCLE
tDRWL
RD
tDRDO
tHSDATI tSSDATI
DATA (IN)
WRITE CYCLE
tDRWL
WR
tDWRO
tSDDATO
DATA (OUT)
tDATTR
Figure 16. Synchronous Read/Write--Bus Master
REV. A
-21-
AD14160/AD14160L
Synchronous Read/Write--Bus Slave
The bus master must meet these (bus slave) timing requirements.
Use these specifications for bus master accesses of a slave's IOP registers or internal memory (in multiprocessor memory space). 40 MHz-5 V Min Max 15.5 + DT/2 5 + DT/2 10 + 5DT/16 -4 - 5DT/16 7.5 + 7DT/16 3 6 1.5 40 MHz-3.3 V Min Max 15.5 + DT/2 5 + DT/2 10 + 5DT/16 -4 - 5DT/16 7.5 + 7DT/16 3 6 1.5
Parameter Timing Requirements: Address, SW Setup Before CLKIN tSADRI tHADRI Address, SW Hold Before CLKIN tSRWLI RD/WR Low Setup Before CLKIN1 tHRWLI RD/WR Low Hold After CLKIN tRWHPI RD/WR Pulse High tSDATWH Data Setup Before WR High tHDATWH Data Hold After WR High Switching Characteristics: Data Delay After CLKIN tSDDATO tDATTR Data Disable After CLKIN2 tDACKAD ACK Delay After Address, SW3 tACKTR ACK Disable After CLKIN3
Units ns ns ns ns ns ns ns
0 - DT/8 -1 - DT/8
20 + 5DT/16 8 - DT/8 10 7 - DT/8
0 - DT/8 -1 - DT/8
20 + 5DT/16 8 - DT/8 10 7 - DT/8
ns ns ns ns
NOTES 1 tSRWLI (min) = 10 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min) = 4.5 + DT/8. 2 See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads. 3 tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have setup times greater than 19 + 3DT/4, then ACK is valid 15 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t ACKTR.
CLKIN
tSADRI tHADRI
ADDRESS SW
tDACKAD
ACK
tACKTR
READ ACCESS
RD
tSRWLI
tHRWLI
tRWHPI
tSDDATO
DATA (OUT)
tDATTR
WRITE ACCESS
WR
tSRWLI
tHRWLI
tRWHPI
tHDATWH tSDATWH
DATA (IN)
Figure 17. Synchronous Read/Write--Bus Slave
-22-
REV. A
AD14160/AD14160L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between multiprocessing ADSP-2106x's (BRx) or a host processor (HBR, HBG). 40 MHz-5 V Parameter Timing Requirements: tHBGRCSV HBG Low to RD/WR/CS Valid1 tSHBRI HBR Setup Before CLKIN2 tHHBRI HBR Hold Before CLKIN2 tSHBGI HBG Setup Before CLKIN tHHBGI HBG Hold Before CLKIN High tSBRI BRx, CPA Setup Before CLKIN3 tHBRI BRx, CPA Hold Before CLKIN High tSRPBAI RPBA Setup Before CLKIN tHRPBAI RPBA Hold Before CLKIN Switching Characteristics: HBG Delay After CLKIN tDHBGO tHHBGO HBG Hold After CLKIN tDBRO BRx Delay After CLKIN tHBRO BRx Hold After CLKIN tDCPAO CPA Low Delay After CLKIN tTRCPA CPA Disable After CLKIN tDRDYCS REDY (O/D) or (A/D) Low from CS and HBR Low4 tTRDYHG REDY (O/D) Disable or REDY (A/D) High from HBG4 tARDYTR REDY (A/D) Disable from CS or HBR High4 Min Max 19.5 + 5DT/4 20 + 3DT/4 14 + 3DT/4 13 + DT/2 6 + DT/2 13.5 + DT/2 6 + DT/2 21.5 + 3DT/4 12 + 3DT/4 21.5 + 3DT/4 12 + 3DT/4 13.5 + DT/2 6 + DT/2 13 + DT/2 6 + DT/2 20 + 3DT/4 14 + 3DT/4 40 MHz-3.3 V Min Max 19.5 + 5DT/4 Units ns ns ns ns ns ns ns ns ns
7.5 - DT/8 -2 - DT/8 8 - DT/8 -2 - DT/8 -2 - DT/8 8.5 - DT/8 5 - DT/8 9.5 43.5 + 27DT/16 11 43.5 + 27DT/16 -2 - DT/8 -2 - DT/8 -2 - DT/8
7.5 - DT/8 8 - DT/8 8.5 - DT/8 5 - DT/8 10.25
ns ns ns ns ns ns ns ns
11
ns
NOTES 1 For first asynchronous access after HBR and CS asserted, ADDR 31-0 must be a non-MMS value 1/2 t CK before RD or WR goes low or by t HBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. 2 Only required for recognition in the current cycle. 3 CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN. 4 (O/D) = open drain, (A/D) = active drive.
REV. A
-23-
AD14160/AD14160L
CLKIN
tSHBRI
HBR
tHHBRI
tHHBGO
HBG (OUT)
tDHBGO
tHBRO
BRx (OUT) CPA (OUT) (O/D)
tDBRO
tDCPAO
tTRCPA
tSHBGI tHHBGI
HBG (IN)
tSBRI tHBRI
BRx (IN) CPA (IN) (O/D) HBR CS
tDRDYCS
REDY (O/D)
tTRDYHG
tARDYTR
REDY (A/D)
tHBGRCSV
HBG (OUT)
RD WR CS
tSRPBAI tHRPBAI
RPBA O/D = OPEN DRAIN, A/D = ACTIVE DRIVE NOTE: HBG WILL BE DELAYED BY n CLOCK CYCLES WHEN WAIT STATES OR BUS LOCK ARE IN EFFECT.
Figure 18. Multiprocessor Bus Request and Host Bus Request
-24-
REV. A
AD14160/AD14160L
Asynchronous Read/Write--Host to AD14160/AD14160L
Use these specifications for asynchronous host processor accesses of an AD14160/AD14160L, after the host has asserted CS and HBR (low). After HBG is returned by the AD14160/AD14160L,
the host can drive the RD and WR pins to access the AD14160/ AD14160L's internal memory or IOP registers. HBR and HBG are assumed low for this timing.
Parameter Lead Cycle Timing Requirements: Address Setup/CS Low Before RD Low1 tSADRDL tHADRDH Address Hold/CS Hold Low After RD RD/WR High Width tWRWH tDRDHRDY RD High Delay After REDY (O/D) Disable tDRDHRDY RD High Delay After REDY (A/D) Disable Switching Characteristics: tSDATRDY Data Valid Before REDY Disable from Low tDRDYRDL REDY (O/D) or (A/D) Low Delay After RD Low REDY (O/D) or (A/D) Low Pulsewidth for Read tRDYPRD tHDARWH Data Disable After RD High Write Cycle Timing Requirements: tSCSWRL CS Low Setup Before WR Low CS Low Hold After WR High tHCSWRH tSADWRH Address Setup Before WR High Address Hold After WR High tHADWRH WR Low Width tWWRL tWRWH RD/WR High Width tDWRHRDY WR High Delay After REDY (O/D) or (A/D) Disable Data Setup Before WR High tSDATWH tHDATWH Data Hold After WR High Switching Characteristics: tDRDYWRL REDY (O/D) or (A/D) Low Delay After WR/CS Low REDY (O/D) or (A/D) Low Pulsewidth for Write tRDYPWR tSRDYCK REDY (O/D) or (A/D) Disable to CLKIN
Min
40 MHz-5 V Max
Min
40 MHz-3.3 V Max
Units
1 1 6 0.5 0.5
1 1 6 0.5 0.5
ns ns ns ns ns
1 11 45 + DT 2 9.5
1 11.5 45 + DT 2 10
ns ns ns ns
0 0.5 6 2.5 7 6 0.5 6 1.5
0 0.5 6 2.5 7 6 0.5 6 1.5
ns ns ns ns ns ns ns ns ns
11 15 0.5 + 7DT/16 8 + 7DT/16
11.5 15 0.5 + 7DT/16 8 + 7DT/16
ns ns ns
NOTE 1 Not required if RD and address are valid t HBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 t CLK before RD or WR goes low or by t HBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be driven during asynchronous host accesses, see Table 8.2 of the ADSP-2106x SHARC User's Manual.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19a. Synchronous REDY Timing
REV. A
-25-
AD14160/AD14160L
READ CYCLE
ADDRESS/CS
tSADRDL
RD
tHADRDH tWRWH
tHDARWH
DATA (OUT)
tSDATRDY tDRDYRDL
REDY (O/D)
tDRDHRDY
tRDYPRD
REDY (A/D)
WRITE CYCLE
ADDRESS
tSCSWRL
CS
tSADWRH tHCSWRH
tHADWRH
tWWRL
WR
tWRWH
tHDATWH tSDATWH
DATA (IN)
tDWRHRDY tDRDYWRL
REDY (O/D)
tRDYPWR
REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19b. Asynchronous Read/Write--Host to ADSP-2106x
-26-
REV. A
AD14160/AD14160L
Three-State Timing--Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin. 40 MHz-5 V Max 40 MHz-3.3 V Min Max 12 + DT/2 6 + DT/2 6 + DT/2
Parameter Timing Requirements: SBTS Setup Before CLKIN tSTSCK tHTSCK SBTS Hold Before CLKIN Switching Characteristics: Address/Select Enable After CLKIN tMIENA tMIENS Strobes Enable After CLKIN1 tMIENHG HBG Enable After CLKIN tMITRA Address/Select Disable After CLKIN tMITRS Strobes Disable After CLKIN1 tMITRHG HBG Disable After CLKIN tDATEN Data Enable After CLKIN2 tDATTR Data Disable After CLKIN2 tACKEN ACK Enable After CLKIN2 tACKTR ACK Disable After CLKIN2 tADCEN ADRCLK Enable After CLKIN tADCTR ADRCLK Disable After CLKIN tMTRHBG Memory Interface Disable Before HBG Low3 tMENHBG Memory Interface Enable After HBG High3
Min
Units ns ns
12 + DT/2
-1.5 - DT/8 -1.5 - DT/8 -1.5 - DT/8 1 - DT/4 2.5 - DT/4 2.5 - DT/4 9 + 5DT/16 0 - DT/8 7.5 + DT/4 -1 - DT/8 -2 - DT/8 -0.5 + DT/8 18.5 + DT 8 - DT/8 7 - DT/8 8.5 - DT/4
-1.25 - DT/8 -1.5 - DT/8 -1.5 - DT/8 1 - DT/4 2.5 - DT/4 2.5 - DT/4 9 + 5DT/16 0 - DT/8 7.5 + DT/4 -1 - DT/8 -2 - DT/8 -0.5 + DT/8 18.5 + DT 8 - DT/8 7 - DT/8 8.5 - DT/4
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES 1 Strobes = RD, WR, SW, PAGE, DMAG. 2 In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 3 Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
CLKIN
tSTSCK
tHTSCK
SBTS
tMIENA, tMIENS, tMIENHG
MEMORY INTERFACE
tMITRA, tMITRS, tMITRHG
tDATEN
DATA
tDATTR
tACKEN
ACK
tACKTR
tADCEN
ADRCLK
tADCTR
HBG
tMENHBG
MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
tMTRHBG
Figure 20. Three-State Timing
REV. A
-27-
AD14160/AD14160L
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0, ACK, and DMAG signals. For Paced Master mode, the data
transfer is controlled by ADDR31-0, RD, WR, MS3-0, and ACK (not DMAG). For Paced Master mode, the "Memory Read-Bus Master", "Memory Write-Bus Master", and "Synchronous Read/Write-Bus Master" timing specifications for ADDR31-0, RD, WR, MS3-0, SW, PAGE, DATA47-0, and ACK also apply.
40 MHz-5 V Parameter Timing Requirements: tSDRLC DMARx Low Setup Before CLKIN 1 tSDRHC DMARx High Setup Before CLKIN 1 DMARx Width Low (Nonsynchronous) tWDR tSDATDGL Data Setup After DMAGx Low2 tHDATIDG Data Hold After DMAGx High Data Valid After DMAGx High2 tDATDRH DMAGx Low Edge to Low Edge tDMARLL tDMARH DMAGx Width High Switching Characteristics: tDDGL DMAGx Low Delay After CLKIN DMAGx High Width tWDGH DMAGx Low Width tWDGL tHDGC DMAGx High Delay After CLKIN tVDATDGH Data Valid Before DMAGx High3 tDATRDGH Data Disable After DMAGx High4 tDGWRF WR Low Before DMAGx Low DMAGx Low Before WR High tDGWRH WR High Before DMAGx High tDGWRR tDGRDF RD Low Before DMAGx Low RD Low Before DMAGx High tDRDGH RD High Before DMAGx High tDGRDR tDGWR DMAGx High to WR, RD, DMAGx Low Address/Select Valid to DMAGx High tDADGH tDDGHA Address/Select Hold After DMAGx High Min 5.5 5.5 6 9 + 5DT/8 2.5 15 + 7DT/8 23 + 7DT/8 6 2.5 Max Min 5.5 5.5 6
40 MHz-3.3 V Max Units ns ns ns ns ns ns ns ns
9 + 5DT/8 15 + 7DT/8 23 + 7DT/8 6
9 + DT/4 6 + 3DT/8 12 + 5DT/8 -2 - DT/8 7 + 9DT/16 -0.5 -0.5 9.5 + 5DT/8 + W 0.5 + DT/16 -0.5 10.5 + 9DT/16 + W -0.5 5 + 3DT/8 + HI 16 + DT -1.5
16 + DT/4
7 - DT/8 8 2.5 3.5 + DT/16 2.5 3.5
9 + DT/4 6 + 3DT/8 12 + 5DT/8 -2 - DT/8 7 + 9DT/16 -0.5 -0.5 9.5 + 5DT/8 + W 0.5 + DT/16 -0.5 10.5 + 9DT/16 + W -0.5 5 + 3DT/8 + HI 16 + DT -1.5
16 + DT/4
7 - DT/8 8 2.5 3.5 + DT/16 2.5 3.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
W = (number of wait states specified in WAIT register) x tCK. HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). NOTES 1 Only required for recognition in the current cycle. 2 tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can be driven t DATDRH after DMARx is brought high. 3 tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t VDATDGH = 7 + 9DT/16 + (n x tCK) where n equals the number of extra cycles that the access is prolonged. 4 See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
-28-
REV. A
AD14160/AD14160L
CLKIN
tSDRLC tDMARLL tSDRHC tWDR
DMARx
tDMARH
tDDGL
DMAGx
tHDGC tWDGL tWDGH
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
tVDATDGH
DATA (FROM ADSP-2106x TO EXTERNAL DRIVE)
tDATRDGH
tDATDRH tSDATDGL
DATA (FROM EXTERNAL DRIVE TO ADSP-2106x)
tHDATIDG
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE)
tDGWRL
tDGWRH
tDGWRR
tDGRDL
tDGRDR
tDRDGH tDADGH
tDDGHA
ADDRESS MSX, SW
* "MEMORY READ - BUS MASTER," "MEMORY WRITE - BUS MASTER," AND "SYNCHRONOUS READ/WRITE - BUS MASTER"
TIMING SPECIFICATIONS FOR ADDR31-0, RD, WR, SW, MS3-0 AND ACK ALSO APPLY HERE.
Figure 21. DMA Handshake Timing
REV. A
-29-
AD14160/AD14160L
Link Ports: 1 x CLK Speed Operation Parameter Receive Timing Requirements: Data Setup Before LCLK Low tSLDCL tHLDCL Data Hold After LCLK Low LCLK Period (1 x Operation) tLCLKIW LCLK Width Low tLCLKRWL tLCLKRWH LCLK Width High Switching Characteristics: tDLAHC LACK High Delay After CLKIN High LACK Low Delay After LCLK High 1 tDLALC LACK Enable from CLKIN tENDLK tTDLK LACK Disable from CLKIN Transmit Timing Requirements: tSLACH LACK Setup Before LCLK High LACK Hold After LCLK High tHLACH Switching Characteristics: LCLK Delay After CLKIN (1 x Operation) tDLCLK tDLDCH Data Delay After LCLK High Data Hold After LCLK High tHLDCH LCLK Width Low tLCLKTWL tLCLKTWH LCLK Width High LCLK Low Delay After LACK High tDLACLK LDAT, LCLK Enable After CLKIN tENDLK tTDLK LDAT, LCLK Disable After CLKIN Link Port Service Request Interrupts: 1 x and 2 x Speed Operations Timing Requirements: tSLCK LACK/LCLK Setup Before CLKIN Low 2 tHLCK LACK/LCLK Hold After CLKIN Low 2 Min 40 MHz-5 V Max Min 40 MHz-3.3 V Max Units
3.5 3 tCK 6 5
3 3 tCK 6 5
ns ns ns ns ns
18 + DT/2 -3 5 + DT/2
29 + DT/2 13.5 20.5 + DT/2
18 + DT/2 -3 5 + DT/2
29 + DT/2 13.5 20.5 + DT/2
ns ns ns ns
18 -7
20 -7
ns ns
16 3.5 -3 (tCK/2) - 2 (tCK/2) - 2 (tCK/2) + 8.5 5 + DT/2 (tCK/2) + 2 (tCK/2) + 2 (3 x tCK/2) + 17.5 20.5 + DT/2 -3 (tCK/2) - 1 (tCK/2) - 1.25 (tCK/2) + 8 5 + DT/2
ns ns ns (tCK/2) + 1.25 ns (tCK/2) + 1 ns (3 x tCK/2) + 18 ns ns 20.5 + DT/2 ns
17 3
10 2
10 2
ns ns
NOTES 1 LACK will go low with t DLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver's link buffer is not about to fill. 2 Only required for interrupt recognition in the current cycle.
-30-
REV. A
AD14160/AD14160L
Link Ports: 2 x CLK Speed Operation Parameter Receive Timing Requirements: Data Setup Before LCLK Low tSLDCL tHLDCL Data Hold After LCLK Low LCLK Period (2 x Operation) tLCLKIW LCLK Width Low tLCLKRWL tLCLKRWH LCLK Width High Switching Characteristics: tDLAHC LACK High Delay After CLKIN High LACK Low Delay After LCLK High 1 tDLALC Transmit Timing Requirements: LACK Setup Before LCLK High tSLACH tHLACH LACK Hold After LCLK High Switching Characteristics: tDLCLK LCLK Delay After CLKIN Data Delay After LCLK High tDLDCH Data Hold After LCLK High tHLDCH tLCLKTWL LCLK Width Low LCLK Width High tLCLKTWH tDLACLK LCLK Low Delay After LACK High Min 40 MHz-5 V Max 40 MHz-3.3 V Min Max Units
2.5 2.25 tCK/2 4.5 4.25
2.25 2.25 tCK/2 5 4
ns ns ns ns ns
18 + DT/2 6
29 + DT/2 16.5
18 + DT/2 6
30 + DT/2 18.5
ns ns
19 -6.75
19 -6.5
ns ns
8.5 3 -2 (tCK/4) - 1 (tCK/4) - 1 (tCK/4) + 9 (tCK/4) + 1 (tCK/4) + 1 (3 x tCL/4) + 17 -2 (tCK/4) - 0.75 (tCK/4) - 1.5 (tCK/4) + 9
8.5 2.75 (tCK/4) + 1.5 (tCK/4) + 1 (3 x tCL/4) + 17
ns ns ns ns ns ns
NOTE 1 LACK will go low with t DLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver's link buffer is not about to fill.
REV. A
-31-
AD14160/AD14160L
TRANSMIT
CLKIN
tDLCLK tLCLKTWH
LCLK 1x OR LCLK 2x
tLCLKTWL
LAST NIBBLE TRANSMITTED
FIRST NIBBLE TRANSMITTED
LCLK INACTIVE (HIGH)
tDLDCH tHLDCH
LDAT(3:0) OUT
tDLACLK tSLACH
LACK (IN) THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
tHLACH
RECEIVE
CLKIN
tLCLKIW tLCLKRWH
LCLK 1x OR LCLK 2x
tLCLKRWL
tHLDCL tSLDCL
LDAT(3:0) IN
tDLAHC
LACK (OUT) LACK GOES LOW ONLY AFFTER THE SECOND NIBBLE IS RECEIVED.
tDLALC
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
CLKIN
tENDLK
LCLK LDAT(3:0) LACK
t TDLK
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
LINK PORT INTERRUPT SETUP TIME
CLKIN
tSLCK
LCLK LACK
t HLCK
Figure 22. Link Ports
-32-
REV. A
AD14160/AD14160L
Serial Ports Parameter External Clock Timing Requirements: tSFSE TFS/RFS Setup Before TCLK/RCLK1 TFS/RFS Hold After TCLK/RCLK1, 2 tHFSE Receive Data Setup Before RCLK1 tSDRE tHDRE Receive Data Hold After RCLK1 TCLK/RCLK Width tSCLKW TCLK/RCLK Period tSCLK Internal Clock Timing Requirements: tSFSI TFS Setup Before TCLK1; RFS Setup Before RCLK1 TFS/RFS Hold After TCLK/RCLK1, 2 tHFSI Receive Data Setup Before RCLK1 tSDRI tHDRI Receive Data Hold After RCLK1 External or Internal Clock Switching Characteristics: RFS Delay After RCLK (Internally Generated RFS) 3 tDFSE RFS Hold After RCLK (Internally Generated RFS) 3 tHFSE External Clock Switching Characteristics: tDFSE TFS Delay After TCLK (Internally Generated TFS) 3 TFS Hold After TCLK (Internally Generated TFS)3 tHFSE Transmit Data Delay After TCLK3 tDDTE tHDTE Transmit Data Hold After TCLK3 Internal Clock Switching Characteristics: TFS Delay After TCLK (Internally Generated TFS) 3 tDFSI TFS Hold After TCLK (Internally Generated TFS)3 tHFSI tDDTI Transmit Data Delay After TCLK3 Transmit Data Hold After TCLK3 tHDTI tSCLKIW TCLK/RCLK Width Enable and Three-State Switching Characteristics: tDDTEN Data Enable from External TCLK3 Data Disable from External TCLK3 tDDTTE Data Enable from Internal TCLK3 tDDTIN tDDTTI Data Disable from Internal TCLK3 TCLK/RCLK Delay from CLKIN tDCLK SPORT Disable After CLKIN tDPTR External Late Frame Sync Switching Characteristics: tDDTLFSE Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 04 tDDTENFS Data Enable from Late FS or MCE = 1, MFD = 04 Min 40 MHz-5 V Max 40 MHz-3.3 V Min Max Units
3.5 4 1.5 4 9.5 tCK
3.5 4 1.5 4 9 tCK
ns ns ns ns ns ns
8 1 3 3
8 1 3 3
ns ns ns ns
13.5 3 3
13.5
ns ns
13.5 3 16.5 5 5 3
13.5 16.5
ns ns ns ns
4.5 -1.5 7.5 0 (SCLK/2) - 2 (SCLK/2) + 2 0 (SCLK/2) - 2.5 -1.5
4.5 7.5 (SCLK/2) + 2.5
ns ns ns ns ns
3.5 11 0 3 22.5 + 3DT/8 17.5
4 11 0 3 22.5 + 3DT/8 17.5
ns ns ns ns ns ns
12.5 3 3.5
13.3
ns ns
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. NOTES 1 Referenced to sample edge. 2 RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge. 3 Referenced to drive edge. 4 MCE = 1, TFS enable and TFS valid follow t DDTLFSE and tDDTENFS.
REV. A
-33-
AD14160/AD14160L
EXTERNAL RFS with MCE = 1, MFD = 0
DRIVE RCLK SAMPLE DRIVE
tHFSE/I tSFSE/I
(SEE NOTE 2)
RFS
tDDTE/I tDDTENFS
DT
tHDTE/I
1ST BIT 2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE TCLK SAMPLE DRIVE
tHFSE/I (SEE NOTE 2) tSFSE/I
TFS
tDDTE/I tDDTENFS
DT
tHDTE/I
1ST BIT 2ND BIT
tDDTLFSE
Figure 23. External Late Frame Sync
-34-
REV. A
AD14160/AD14160L
DATA RECEIVE- INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA RECEIVE- EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
RCLK RCLK
tSCLKW
tDFSE tHFSE
RFS
tSFSI
tHFSI
RFS
tDFSE tHFSE
tSFSE
tHFSE
tSDRI
DR
tHDRI
DR
tSDRE
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT- INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT- EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
TCLK TCLK
tSCLKW
tHFSI
TFS
tDFSI tSFSI tHFSI
TFS
tDFSE tHFSE
tSFSE
tHFSE
tHDTI
DT
tDDTI
tHDTE
DT
tDDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
TCLK (EXT)
TCLK / RCLK
tDDTEN
DT
DRIVE EDGE DRIVE EDGE
tDDTTE
TCLK (INT)
TCLK / RCLK
tDDTIN tDDTTI
DT
CLKIN
CLKIN
tDPTR
TCLK, RCLK TFS, RFS, DT SPORT DISABLE DELAY FROM INSTRUCTION SPORT ENABLE AND THREE-STATE LATENCY IS TWO CYCLES
tSTFSCK
TFS (EXT)
tHTFSCK
tDCLK
TCLK (INT) RCLK (INT) LOW TO HIGH ONLY
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR MESH MULTIPROCESSING.
Figure 24. Serial Ports
REV. A
-35-
AD14160/AD14160L
JTAG Test Access Port and Emulation
Parameter Timing Requirements: tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS System Inputs Setup Before TCK Low1 tHSYS System Inputs Hold After TCK Low1 tTRSTW TRST Pulsewidth Switching Characteristics: tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low 2
Min tCK 5.5 6.5 8 18.5 4tCK
40 MHz-5 V Max
40 MHz-3.3 V Min Max tCK 5.5 6.5 8 19 4tCK
Units ns ns ns ns ns ns
13.5 20
13.5 20
ns ns
NOTES 1 System Inputs = DATA 47-0, ADDR 31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR 6-1, RPBA, IDy2-0, IRQ 2-0, FLAGy3-0, DRy0, DyR1, TCLKy0, TCLKy1, RCLKy0, RCLKy1, TFSy0, TFSy1, RFSy0, RFSy1, LxDAT 3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET. 2 System Outputs = DATA 47-0, ADDR 31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR 6-1, CPA, FLAG2-0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS.
tTCK
TCK
tSTAP
TMS TDI
tHTAP
tDTDO
TDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure 25. IEEE 11499.1 JTAG Test Access Port
-36-
REV. A
AD14160/AD14160L
OUTPUT DRIVE CURRENTS POWER DISSIPATION
Figure 26 shows typical I-V characteristics for the output drivers of the ADSP-2106x. The curves represent the current drive capability of the output drivers as a function of output voltage.
100 75 50
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Internal power dissipation is calculated in the following way: PINT = IDDIN x VDD The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on:
SOURCE CURRENT - mA
25 0 -25 -50 -75 -100 -125 -150 -175 -200 0 0.75
5.25V, -40 C 5.0V, +25C 4.75V, +85C
4.75V, +85C 5.0V, +25C 5.25V, -40C
- the number of output pins that switch during each cycle (O) - the maximum frequency at which they can switch (f) - their load capacitance (C) - their voltage swing (VDD) and is calculated by: PEXT = O x C x VDD2 x f The load capacitance should include the processor's package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2tCK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. Example: Estimate PEXT with the following assumptions: -A system with one bank of external data memory RAM (32-bit). -Four 128K x 8 RAM chips are used, each with a load of 10 pF. -External data memory writes occur every other cycle, a rate -of 1/(4tCK), with 50% of the pins switching. -The instruction cycle rate is 40 MHz (tCK = 25 ns) and -VDD = 3.3 V. The PEXT equation is calculated for each class of pins that can drive:
3 3.5
1.50 2.25 3.00 3.75 SOURCE VOLTAGE - V
4.50
5.25
Figure 26. ADSP-2106x Typical Drive Currents (VDD = 5 V)
120 100 80 3.3V, +25C 3.6V, -40C 3.0V, +85 C
SOURCE CURRENT - mA
60 40 20 0 -20 -40 -60 -80 3.0V, +85C VOH
3.3V, +25C 3.6V, -40C
-100 -120 0 0.5 1
VOL 1.5 2 2.5 SOURCE VOLTAGE - V
Figure 27. ADSP-2106x Typical Drive Currents (VDD = 3.3 V)
Pin Type Address MS0 WR Data ADRCLK
# of Pins 15 1 1 32 1
% Switching 50 0 - 50 -
C x 55 pF x 55 pF x 55 pF x 25 pF x 15 pF x 20 MHz x 20 MHz x 40 MHz x 20 MHz x 40 MHz
VDD2 = PEXT x 10.9 V x 10.9 V x 10.9 V x 10.9 V x 10.9 V = 0.089 W = 0.00 W = 0.024 W = 0.087 W = 0.007 W
PEXT (3.3 V)= 0.207 W PEXT (5 V)= 0.476 W
A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: PTOTAL = PEXT + (IDDIN2 x 5.0 V ) Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Also note that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.
REV. A
-37-
AD14160/AD14160L
TEST CONDITIONS Output Disable Time
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by V is dependent on the capacitive load, CL, and the load current, IL. This decay time can be approximated by the following equation:
REFERENCE SIGNAL
tMEASURED tDIS
VOH (MEASURED) VOH (MEASURED) - V VOL (MEASURED) + V VOL (MEASURED)
tENA
VOH (MEASURED)
2.0V 1.0V
t DECAY
C V =L IL
tDECAY
OUTPUT STOPS DRIVING
VOL (MEASURED)
The output disable time, tDIS, is the difference between tMEASURED and tDECAY as shown in Figure 28. The time tMEASURED is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage. tDECAY is calculated with test loads CL and IL, and with V equal to 0.5 V.
Output Enable Time
OUTPUT STARTS DRIVING HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V
Figure 28. Output Enable/Disable
IOL
Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time, tENA, is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram (Figure 28). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
Example System Hold Time Calculation
TO OUTPUT PIN
+1.5V 50pF
IOH
To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-2106x's output voltage and the input threshold for the device requiring the hold time. A typical V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (i.e., tHDWD for the write cycle).
Figure 29. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
INPUT OR OUTPUT 1.5V 1.5V
Figure 30. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
Capacitive Loading
Output delays and holds are based on standard capacitive loads: 50 pF on all pins (see Figure 29). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for loads other than the nominal value of 50 pF. Figures 31, 32, 33 and 34 show how output rise time varies with capacitance. Figures 35 and 36 graphically show how output delays and holds vary with load capacitance. (Note that these graphs or derating does not apply to output disable delays; see the previous section Output Disable Time under Test Conditions.) The graphs of Figures 31 through 36 may not be linear outside the ranges shown.
-38-
REV. A
AD14160/AD14160L
16.0 RISE AND FALL TIMES - ns (0.8V - 2.0V) 14.0
RISE AND FALL TIMES - ns (0.5V - 4.5V, 10% - 90%) 9 8 7 6 5 4 3 2 1 0 FALL TIME RISE TIME Y = 0.0305X + 0.24 Y = 0.0391X + 0.36
12.0 RISE TIME 10.0 8.0 6.0 4.0 2.0 0 Y = 0.0031X + 1.1 Y = 0.005X + 3.7 FALL TIME
0
20
40
60 80 100 120 140 LOAD CAPACITANCE - pF
160
180
200
0
20
40
60
80
100
120
140
160
180
200
LOAD CAPACITANCE - pF
Figure 31. Typical Output Rise Time (10%-90%) vs. Load Capacitance (VDD = 5 V)
18
Figure 34. Typical Output Rise Time (0.8 V -2.0 V) vs. Load Capacitance (VDD = 3.3 V)
5
RISE AND FALL TIMES - ns (10% - 90%)
16 14 Y = 0.0796X + 1.17 12 10 RISE TIME 8 6 4 2 0 0 20 40 60 80 100 120 140 160 180 200 LOAD CAPACITANCE - pF -1 FALL TIME Y = 0.0467X + 0.55
OUTPUT DELAY OR HOLD - ns
4
3 Y = 0.03X -1.45 2
1
NOMINAL
25
50
75 100 125 150 LOAD CAPACITANCE - pF
175
200
Figure 32. Typical Output Rise Time (10%-90%) vs. Load Capacitance (VDD = 3.3 V)
3.5
RISE AND FALL TIMES - ns (0.8V - 2.0V)
Figure 35. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (VDD = 5 V)
5
2.5 RISE TIME 2.0 Y = 0.009X + 1.1 1.5
OUTPUT DELAY OR HOLD - ns
3.0
4
Y = 0.0329X -1.65
3
2
1
1.0 Y = 0.005X + 0.6 0.5 0 0 20 40
FALL TIME
NOMINAL
-1
60 80 100 120 140 LOAD CAPACITANCE - pF 160 180 200
25
50
75 100 125 150 LOAD CAPACITANCE - pF
175
200
Figure 33. Typical Output Rise Time (0.8 V-2.0 V) vs. Load Capacitance (VDD = 5 V)
Figure 36. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (VDD = 3.3 V)
REV. A
-39-
AD14160/AD14160L
ASSEMBLY RECOMMENDATIONS Socket Information Signal Pad Assignment Topology
Standard sockets are available from 3M and Plastronics. The 3M socket used is the BGA III style. The customer must specify how they want the socket populated with pins and a slight modification is required to compensate for the tolerance of the package thickness.
PCB Board Layout
A classical dog bone style pad should be used. A solder pad diameter of 0.65 mm is recommended. The pad should be nonsoldermask defined.
NON-SOLDERMASK DEFINED PAD
The AD14160/AD14160L signal pad assignments were carefully analyzed for improved board routing and maximum reliability. By restricting the required 432 I/O to the inner 25 mm circle, TCE mismatch concerns are minimized. (BGA ball patterns of 25 mm size are well characterized and documented.) The signal I/O is carefully placed and grouped to minimize pin escape difficulties in routing. Redundant power/ground contact pads are also provided (but not required) to improve the thermal performance and the ground bounce performance of the package (see Figure 42).
DENSITY IMPROVEMENTS
In addition to careful considerations to performance characteristics such as ground bounce, signal quality, and noise isolation, the AD14160/AD14160L also provides significant density advantages.
Board Area Reduction
SOLDERMASK
The minimally packaged AD14160/AD14160L CBGA reduces required board area by approximately 75%.
Figure 37.
Solder Paste Printing
3.50 IN SQ
DISCRETE SHARC
DISCRETE SHARC
A solder paste print of 0.7 mm diameter with thickness of 0.15 to 0.2 mm is recommended. Normal solder paste alloy can be used, i.e., 60/40, 63/37, etc.
Reflow Profile
The profile shown below is recommended.
MEASUREMENT POINT BGA PCB 220
TEMPERATURE - C
QUAD SHARC BGA MCM DISCRETE SHARC
PEAK 220
10 C
PIN ONE
200 160 200 C 50 10 C/MIN 160 150
200 170 C -40 10 C/MIN
1.850 IN SQ
Figure 39.
Embedded Wiring
120 30 SEC 150 160 C 100 150 C 50 10 C/MIN 60 10 SEC OVER 200 C
100
TIME - Sec
Figure 38.
Forty feet of optimized routing is embedded in four integrated signal routing layers (in addition to power and ground planes). This eliminated hundreds of feet of multiprocessing interconnect on the target PCB; thereby, also reducing board cost and required routing layers.
-40-
REV. A
AD14160/AD14160L
GROUND BOUNCE ESTIMATE
Ground bounce diminishes noise margins in a system and must be held as low as possible. Ground bounce results from switching output pins from a high to a low state with the ensuing discharge current creating a voltage across the parasitic inductance of the MCM's ground pins (and to a lesser extent across the wirebond wires connecting the ground pads). A useful model for calculating the level of ground bounce is shown below (Johnson, Howard W. and Graham, Martin, "High-Speed Digital Design," Prentice Hall p67, 1993).
VDD
In the Quad-SHARC module, the worse case ground bounce condition occurs during an external memory operation in which 86 signals switch simultaneously from high to low. Because of the ground planes embedded within the substrate of the module, the effective ground pin inductance is found by dividing the CBGA's single ground pin inductance, estimated to be about 3 nH, by the 64 ground pins resulting in LGND = 0.05 nH. Typical output fall times for varying load conditions can be obtained from this data sheet. The induced voltage generated by the switching currents is given by d (I ) VGND = LGND dt DISCHARGE Assuming the voltage waveform is an integrated Gaussian pulse, the peak amplitude is approximated by
SHARC DIE
VIN
|VGND| max = LGND 1.52V C. T10-902
IDISCHARGE LOAD C
Calculated ground bounce maximum values for the CBGA module are listed below. Load per Output (pF) 20 100 200 Fall Time (ns) 1.8 4.2 7.4 Ground Bounce (V) 0.161 0.148 0.095
VGND
GROUND PIN INDUCTANCE LGND
SYSTEM GROUND PLANE
Figure 40.
REV. A
-41-
AD14160/AD14160L
Thermal Characteristics Metal Coverage Per Layer
The AD14160/AD14160L is packaged in a 452-lead ceramic ball grid array (CBGA). The package is optimized for thermal conduction through the core (base of the package) down to the mounting surface. The AD14160/AD14160L is specified for a case temperature (TCASE). Design of the mounting surface and attachment material should be such that TCASE is not exceeded. JC = 0.36C/W
Thermal Cross-Section
Layer VDD SIG2 SIG3 GND SIG4 SIG5 BASE
(Assume Uniformly Distributed)
Percent Metal (1 Mil Thick) 87 12 12 89 14 13 91
The data below, together with the detailed mechanical drawings at the end of the data sheet, allows for constructing simple thermal models for further analysis within targeted systems. The top layer of the package, where the die are mounted, is a metal VDD layer. The approximate metal area coverage from the metal planes and routing layers is estimated below.
Thermal Conductivity
Material Ceramic Kovar Tungsten Thermoplastic Silicon
Thermal Conductivity W/cm C 0.18 0.14 1.78 0.03 1.45
KOVAR LID 0.015 IN SUB-PAD SIGI SILICON DIE 19 MILS THERMOPLASTIC THICKNESS 5 MILS VDD SIG2 SIG3 GND SIG4 SIG5 BASE DBGA PADS
KOVAR SEAL RING HEIGHT = 50 MILS SEAL RING METALIZATION
CERAMIC LAYER 28 MILS (2 LAYERS 14 MILS EACH) CERAMIC LAYER 6 MILS CERAMIC LAYER 6 MILS CERAMIC LAYER 10 MILS CERAMIC LAYER 4 MILS CERAMIC LAYER 10 MILS CERAMIC LAYER 10 MILS CERAMIC LAYER 4 MILS CERAMIC LAYER 10 MILS CERAMIC LAYER 4 MILS CERAMIC LAYER 8 MILS
Figure 41.
-42-
REV. A
AD14160/AD14160L
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B CD E F GH J K LM NP R TU VW YAA AB AA CD AAAAAAAAAA EFGHJKLMNP AA RT
ADDRESS NOTE: PADS OUTSIDE THE DARK BORDER ARE REDUNDANT OR NOT REQUIRED. THE MODULE IS PRODUCTION TESTED WITH ONLY THOSE SIGNALS INSIDE THE DARK BORDER. DATA LINKS SERIAL PORTS
CONTROLS, MISC VDD GND UNUSED
Figure 42. Board Footprint for AD14160/AD14160L Quad SHARC BGA
REV. A
-43-
AD14160/AD14160L
MECHANICAL CHARACTERISTICS
Lid Deflection Analysis
25
1.850 0.012 SQ.
0.670 0.007 4
0.653 0.007 4 0.195
20
DEFLECTION - Mils
15
0.616
0.633
10
0.188 0.188 0.230 1.790 1.710 1.680
4.87379679 2.41724599 0.69766043 EXTERNAL PRESSURE - lbs/in2
5
0 7.33034759
0.024 TYP 0.012 REF 4 0.060 4 0.008 REF
Figure 43. Deflection (mils) vs. External Pressure
Mechanical Model
The data below, together with the detailed mechanical drawings at the end of the data sheet, allows for construction of simple mechanical models for further analysis within targeted systems.
Mechanical Properties
Material Ceramic Kovar Tungsten Thermoplastic Silicon
Modulus of Elasticity 26 x 103 kg/mm2 14.1 x 103 kg/mm2 35 x 103 kg/mm2 279 kg/mm2 11 x 103 kg/mm2
The following pages list two separate pin listings. The first is ordered by pin number and the second is an alphabetical list by pin name. Note that there are many not required or redundant pins beyond the standard package 452 leads. These pins are noted in parentheses. For example: (GND), (VDD), (unused), (TEST). These pins are extraneous and only the redundant (GND) and (VDD) should be connected if desired.
452-LEAD CBGA PIN CONFIGURATION
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
PIN A1 INDEX
BOTTOM VIEW
-44-
REV. A
AD14160/AD14160L
PIN CONFIGURATIONS (Pin Order Listing)
Pin No Pin Name Pin No C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 Pin Name (GND) (GND) (unused) (VDD) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (GND) (VDD) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (GND) (unused) (VDD) (GND) (GND) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (VDD) (VDD) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (GND) Pin No. E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 Pin Name (GND) (unused) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (VDD) (VDD) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (unused) (GND) (GND) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (TEST12) (TEST12) (TEST13) (TEST13) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (GND) Pin No G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 Pin Name (GND) (unused) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) GND LB1DAT2 LB1DAT3 RFSA1 RFSA0 VDD (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (unused) (GND) (GND) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (TEST11) LB1ACK LB1CLK LB1DAT0 LB1DAT1 LB2DAT2 LB2DAT3 RCLKA1 RCLKA0 REDY VDD GND VDD (TEST14) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (GND) Pin No. J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 Pin Name (GND) (unused) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (TEST11) DATA10 LB2ACK LB2CLK LB2DAT0 LB2DAT1 GND VDD DRA1 DRA0 ACK PAGE GND VDD GND (TEST14) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (unused) (GND) (GND) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) GND DATA21 DATA11 LB3ACK LB3CLK LB3DAT0 LB3DAT1 LB3DAT2 LB3DAT3 TFSA1 TFSA0 CSA LA1ACK LA1CLK LA1DAT0 LA1DAT1 LA1DAT2 LA1DAT3 (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (GND) Pin No. L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 L34 L35 L36 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 M35 M36 Pin Name (GND) (unused) (unused) (unused) (GND) (unused) (GND) (unused) (TEST10) DATA30 DATA22 DATA12 LB4ACK LB4CLK LB4DAT0 LB4DAT1 LB4DAT2 LB4DAT3 TCLKA1 TCLKA0 RESET LA2ACK LA2CLK LA2DAT0 LA2DAT1 LA2DAT2 LA2DAT3 (TEST15) (unused) (GND) (unused) (GND) (unused) (unused) (unused) (GND) (GND) (unused) (unused) (GND) (unused) (GND) (unused) (TEST10) RFSB0 DATA31 DATA23 DATA13 DATA2 DATA0 DMAG1 DMAR1 DMAR2 VDD DTA1 DTA0 CPAA LA3ACK LA3CLK LA3DAT0 LA3DAT1 LA3DAT2 LA3DAT3 VDD (TEST15) (unused) (GND) (unused) (GND) (unused) (unused) (GND)
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34
(GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND)
B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35
(GND) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (GND)
REV. A
-45-
AD14160/AD14160L
PIN CONFIGURATIONS (Pin Order Listing Continued)
Pin No N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 N32 N33 N34 N35 N36 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 Pin Name (GND) (unused) (unused) (unused) (GND) (unused) (GND) VDD RCLKB0 DATA32 DATA24 DATA14 DATA3 DATA1 DMAG2 SBTS (unused) (unused) (unused) (unused) (unused) LA4ACK LA4CLK LA4DAT0 LA4DAT1 LA4DAT2 LA4DAT3 GND VDD (GND) (unused) (GND) (unused) (unused) (unused) (GND) (GND) (unused) (unused) (GND) (unused) (GND) (unused) RFSB1 DRB0 DATA33 DATA25 DATA15 DATA4 GND GND IDB0 IDB1 IDB2 (unused) (unused) (unused) GND GND GND GND GND GND IDA1 IDA2 (unused) (GND) (unused) (GND) (unused) (unused) (GND) Pin No R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 Pin Name (GND) (unused) (unused) (unused) (GND) (unused) (GND) RCLKB1 TFSB0 DATA34 DATA26 DATA16 DATA5 GND GND GND IRQB0 IRQB1 IRQB2 GND GND GND RPBA MS0 MS1 MS2 MS3 IDA0 LBOOTA (GND) (unused) (GND) (unused) (unused) (unused) (GND) (GND) (unused) (unused) (GND) (unused) (GND) VDD DRB1 TCLKB0 DATA35 DATA27 DATA17 DATA6 VDD GND GND GND GND GND (unused) (unused) (unused) (unused) ADDR28 ADDR29 ADDR30 ADDR31 IRQA0 EBOOTA GND (GND) (unused) (GND) (unused) (unused) (GND) Pin No. U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 V35 V36 Pin Name (GND) (unused) (unused) (unused) (unused) (TEST9) GND TFSB1 DTB0 DATA36 CLKIN DATA18 DATA7 VDD GND TIMEXPB VDD VDD VDD VDD VDD GND GND ADDR24 ADDR25 ADDR26 ADDR27 IRQA2 IRQA1 TDOA (TEST16) (unused) (unused) (unused) (unused) (GND) (GND) (GND) (VDD) (VDD) (VDD) (TEST9) CSB TCLKB1 DATA45 DATA37 DATA28 DATA19 DATA8 FLAGB0 FLAGB1 FLAGB2 FLAGB3 VDD VDD GND VDD BMSA GND ADDR20 ADDR21 ADDR22 ADDR23 FLAGA0 FLAGA1 TIMEXPA (TEST16) (VDD) (VDD) (GND) (VDD) (GND) Pin No W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W33 W34 W35 W36 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Pin Name (GND) (GND) (VDD) (VDD) (VDD) (TEST8) GND DTB1 DATA46 DATA38 DATA29 DATA20 DATA9 (unused) (unused) GND VDD VDD VDD GND VDD VDD GND ADDR16 ADDR17 ADDR18 ADDR19 FLAGA3 FLAGA2 TDI (TEST1) (VDD) (VDD) (GND) (VDD) (GND) (GND) (unused) (unused) (unused) (unused) (TEST8) VDD SW BR1 DATA47 DATA43 DATA41 DATA39 (unused) (unused) GND GND VDD VDD VDD VDD GND GND ADDR12 ADDR13 ADDR14 ADDR15 FLAGD0 IRQD0 GND (TEST1) (unused) (unused) (unused) (unused) (GND) Pin No. AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 AA35 AA36 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34 AB35 AB36 Pin Name (GND) (unused) (unused) (GND) (unused) (GND) GND HBR BR2 CPAB DATA44 DATA42 DATA40 (unused) (unused) GND GND GND GND GND VDD VDD GND ADDR8 ADDR9 ADDR10 ADDR11 FLAGD1 IRQD1 VDD (GND) (unused) (GND) (unused) (unused) (GND) (GND) (unused) (unused) (unused) (GND) (unused) (GND) HBG BR3 GND RFSC1 RFSC0 TDOB (unused) (unused) GND GND GND GND VDD VDD VDD VDD ADDR4 ADDR5 ADDR6 ADDR7 FLAGD2 IRQD2 (GND) (unused) (GND) (unused) (unused) (unused) (GND) Pin No. AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 AD35 AD36 Pin Name (GND) (unused) (unused) (GND) (unused) (GND) (unused) GND BR4 FLAGC0 RCLKC1 RCLKC0 ADRCLK VDD VDD VDD VDD GND GND GND VDD VDD TIMEXPC ADDR0 ADDR1 ADDR2 ADDR3 FLAGD3 VDD (unused) (GND) (unused) (GND) (unused) (unused) (GND) (GND) (unused) (unused) (unused) (GND) (unused) (GND) VDD BR5 FLAGC1 DRC1 DRC0 CPAC CSC EMU GND TMS TRST RFSD1 RFSD0 BMSBCD LD1ACK LD1CLK LD1DAT0 LD1DAT1 LD1DAT2 LD1DAT3 TIMEXPD GND (GND) (unused) (GND) (unused) (unused) (unused) (GND)
-46-
REV. A
AD14160/AD14160L
PIN CONFIGURATIONS (Pin Order Listing Continued)
Pin No AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 AE35 AE36 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AF36 Pin Name (GND) (unused) (unused) (GND) (unused) (GND) (unused) (TEST7) BR6 FLAGC2 TFSC1 TFSC0 LC1ACK LC1CLK LC1DAT0 LC1DAT1 LC1DAT2 LC1DAT3 RCLKD1 RCLKD0 WR LD2ACK LD2CLK LD2DAT0 LD2DAT1 LD2DAT2 LD2DAT3 VDD (TEST2) (unused) (GND) (unused) (GND) (unused) (unused) (GND) (GND) (unused) (unused) (unused) (GND) (unused) (GND) (unused) (TEST7) FLAGC3 TCLKC1 TCLKC0 LC2ACK LC2CLK LC2DAT0 LC2DAT1 LC2DAT2 LC2DAT3 DRD1 DRD0 RD LD3ACK LD3CLK LD3DAT0 LD3DAT1 LD3DAT2 LD3DAT3 (TEST2) (unused) (GND) (unused) (GND) (unused) (unused) (unused) (GND) Pin No AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 AG35 AG36 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 AH35 AH36 Pin Name (GND) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) GND DTC1 DTC0 IRQC0 IRQC1 IRQC2 IDC0 IDC1 IDC2 TFSD1 TFSD0 CSD LD4ACK LD4CLK LD4DAT0 LD4DAT1 LD4DAT2 LD4DAT3 (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (GND) (GND) (unused) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (TEST6) VDD LC3ACK LC3CLK LC3DAT0 LC3DAT1 LC3DAT2 LC3DAT3 TCLKD1 TCLKD0 IDD0 IDD1 IDD2 EBOOTBCD TDOC (TEST3) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (unused) (GND) Pin No. AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AK35 AK36 Pin Name (GND) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (TEST6) LC4ACK LC4CLK LC4DAT0 LC4DAT1 LC4DAT2 LC4DAT3 DTD1 DTD0 CPAD TDO LBOOTBCD TCK (TEST3) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (GND) (GND) (unused) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) GND VDD GND VDD VDD GND (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (unused) (GND) Pin No AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 AL36 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 Pin Name (GND) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (TEST5) (TEST5) (TEST4) (TEST4) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (GND) (GND) (unused) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (VDD) (VDD) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (unused) (GND) Pin No. AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 AP35 AP36 Pin Name (GND) (unused) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (VDD) (VDD) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (GND) (unused) (unused) (GND) (GND) (GND) (unused) (VDD) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (GND) (VDD) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (GND) (unused) (VDD) (GND) Pin No. AR2 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 Pin Name (GND) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (GND)
AT3 AT4 AT5 AT6 AT7 AT8 AT9 AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34
(GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND)
REV. A
-47-
AD14160/AD14160L
PIN CONFIGURATIONS (Alphabetical Listing)
Pin Name ACK ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 ADDR26 ADDR27 ADDR28 ADDR29 ADDR30 ADDR31 ADRCLK BMSA BMSBCD BR1 BR2 BR3 BR4 BR5 BR6 CLKIN CPAA CPAB CPAC CPAD CSA CSB CSC CSD DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 Pin No. J21 AC24 AC25 AC26 AC27 AB24 AB25 AB26 AB27 AA24 AA25 AA26 AA27 Y24 Y25 Y26 Y27 W24 W25 W26 W27 V24 V25 V26 V27 U24 U25 U26 U27 T24 T25 T26 T27 AC13 V22 AD21 Y9 AA9 AB9 AC9 AD9 AE9 U11 M21 AA10 AD13 AJ21 K21 V7 AD14 AG21 M14 N14 M13 N13 P13 R13 T13 U13 V13 W13 J12 K12 L12 M12 N12 P12 R12 T12 U12 V12 W12 Pin Name DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DATA32 DATA33 DATA34 DATA35 DATA36 DATA37 DATA38 DATA39 DATA40 DATA41 DATA42 DATA43 DATA44 DATA45 DATA46 DATA47 DMAG1 DMAG2 DMAR1 DMAR2 DRA0 DRA1 DRB0 DRB1 DRC0 DRC1 DRD0 DRD1 DTA0 DTA1 DTB0 DTB1 DTC0 DTC1 DTD0 DTD1 EBOOTA EBOOTBCD EMU FLAGA0 FLAGA1 FLAGA2 FLAGA3 FLAGB0 FLAGB1 FLAGB2 FLAGB3 FLAGC0 FLAGC1 FLAGC2 FLAGC3 FLAGD0 FLAGD1 FLAGD2 FLAGD3 GND GND GND GND GND GND Pin No. K11 L11 M11 N11 P11 R11 T11 V11 W11 L10 M10 N10 P10 R10 T10 U10 V10 W10 Y13 AA13 Y12 AA12 Y11 AA11 V9 W9 Y10 M15 N15 M16 M17 J20 J19 P9 T8 AD12 AD11 AF20 AF19 M20 M19 U9 W8 AG12 AG11 AJ20 AJ19 T29 AH24 AD15 V28 V29 W29 W28 V14 V15 V16 V17 AC10 AD10 AE10 AF10 Y28 AA28 AB28 AC28 G16 H23 J17 J23 J25 K10 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HBG HBR IDA0 IDA1 IDA2 IDB0 IDB1 IDB2 IDC0 IDC1 IDC2 IDD0 IDD1 IDD2 Pin No. N28 P14 P15 P22 P23 P24 P25 P26 P27 R14 R15 R16 R20 R21 R22 T15 T16 T17 T18 T19 T30 U7 U15 U22 U23 V20 V23 W7 W16 W20 W23 Y16 Y17 Y22 Y23 Y30 AA7 AA16 AA17 AA18 AA19 AA20 AA23 AB10 AB16 AB17 AB18 AB19 AC8 AC18 AC19 AC20 AD16 AD29 AG10 AK16 AK18 AK21 AB8 AA8 R28 P28 P29 P16 P17 P18 AG16 AG17 AG18 AH21 AH22 AH23 Pin Name IRQA0 IRQA1 IRQA2 IRQB0 IRQB1 IRQB2 IRQC0 IRQC1 IRQC2 IRQD0 IRQD1 IRQD2 LA1ACK LA1CLK LA1DAT0 LA1DAT1 LA1DAT2 LA1DAT3 LA2ACK LA2CLK LA2DAT0 LA2DAT1 LA2DAT2 LA2DAT3 LA3ACK LA3CLK LA3DAT0 LA3DAT1 LA3DAT2 LA3DAT3 LA4ACK LA4CLK LA4DAT0 LA4DAT1 LA4DAT2 LA4DAT3 LB1ACK LB1CLK LB1DAT0 LB1DAT1 LB1DAT2 LB1DAT3 LB2ACK LB2CLK LB2DAT0 LB2DAT1 LB2DAT2 LB2DAT3 LB3ACK LB3CLK LB3DAT0 LB3DAT1 LB3DAT2 LB3DAT3 LB4ACK LB4CLK LB4DAT0 LB4DAT1 LB4DAT2 LB4DAT3 LBOOTA LBOOTBCD LC1ACK LC1CLK LC1DAT0 LC1DAT1 LC1DAT2 LC1DAT3 LC2ACK LC2CLK LC2DAT0 LC2DAT1 Pin No. T28 U29 U28 R17 R18 R19 AG13 AG14 AG15 Y29 AA29 AB29 K22 K23 K24 K25 K26 K27 L22 L23 L24 L25 L26 L27 M22 M23 M24 M25 M26 M27 N22 N23 N24 N25 N26 N27 H13 H14 H15 H16 G17 G18 J13 J14 J15 J16 H17 H18 K13 K14 K15 K16 K17 K18 L13 L14 L15 L16 L17 L18 R29 AJ23 AE13 AE14 AE15 AE16 AE17 AE18 AF13 AF14 AF15 AF16 Pin Name LC2DAT2 LC2DAT3 LC3ACK LC3CLK LC3DAT0 LC3DAT1 LC3DAT2 LC3DAT3 LC4ACK LC4CLK LC4DAT0 LC4DAT1 LC4DAT2 LC4DAT3 LD1ACK LD1CLK LD1DAT0 LD1DAT1 LD1DAT2 LD1DAT3 LD2ACK LD2CLK LD2DAT0 LD2DAT1 LD2DAT2 LD2DAT3 LD3ACK LD3CLK LD3DAT0 LD3DAT1 LD3DAT2 LD3DAT3 LD4ACK LD4CLK LD4DAT0 LD4DAT1 LD4DAT2 LD4DAT3 MS0 MS1 MS2 MS3 PAGE RCLKA0 RCLKA1 RCLKB0 RCLKB1 RCLKC0 RCLKC1 RCLKD0 RCLKD1 RD REDY RESET RFSA0 RFSA1 RFSB0 RFSB1 RFSC0 RFSC1 RFSD0 RFSD1 RPBA SBTS SW TCK TCLKA0 TCLKA1 TCLKB0 TCLKB1 TCLKC0 TCLKC1 Pin No. AF17 AF18 AH13 AH14 AH15 AH16 AH17 AH18 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AD22 AD23 AD24 AD25 AD26 AD27 AE22 AE23 AE24 AE25 AE26 AE27 AF22 AF23 AF24 AF25 AF26 AF27 AG22 AG23 AG24 AG25 AG26 AG27 R24 R25 R26 R27 J22 H20 H19 N9 R8 AC12 AC11 AE20 AE19 AF21 H21 L21 G20 G19 M9 P8 AB12 AB11 AD20 AD19 R23 N16 Y8 AJ24 L20 L19 T9 V8 AF12 AF11 Pin Name TCLKD0 TCLKD1 TDI TDO TDOA TDOB TDOC TFSA0 TFSA1 TFSB0 TFSB1 TFSC0 TFSC1 TFSD0 TFSD1 TIMEXPA TIMEXPB TIMEXPC TIMEXPD TMS TRST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD WR Pin No. AH20 AH19 W30 AJ22 U30 AB13 AH25 K20 K19 R9 U8 AE12 AE11 AG20 AG19 V30 U16 AC23 AD28 AD17 AD18 G21 H22 H24 J18 J24 M18 M28 N8 N29 T7 T14 U14 U17 U18 U19 U20 U21 V18 V19 V21 W17 W18 W19 W21 W22 Y7 Y18 Y19 Y20 Y21 AA21 AA22 AA30 AB20 AB21 AB22 AB23 AC14 AC15 AC16 AC17 AC21 AC22 AC29 AD8 AE28 AH12 AK17 AK19 AK20 AE21
-48-
REV. A
AD14160/AD14160L
PIN CONFIGURATIONS (Alphabetical Listing Continued)
Pin Name (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) Pin No. A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 B2 B35 C1 C2 C18 C33 C36 D1 D4 D6 D8 D10 D12 D14 D16 D21 D23 D25 D27 D29 D31 D33 D36 E1 E5 E7 E9 E11 E13 E15 E22 E24 E26 E28 E30 E32 E36 F1 F4 F6 Pin Name (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) Pin No. F8 F10 F12 F14 F16 F21 F23 F25 F27 F29 F31 F33 F36 G1 G5 G7 G9 G11 G13 G15 G22 G24 G26 G28 G30 G32 G36 H1 H4 H6 H8 H10 H27 H29 H31 H33 H36 J1 J5 J7 J9 J28 J30 J32 J36 K1 K4 K6 K8 K29 K31 K33 K36 L1 L5 L7 L30 L32 L36 M1 M4 M6 M31 M33 M36 N1 N5 N7 N30 N32 N36 P1 Pin Name (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) Pin No. P4 P6 P31 P33 P36 R1 R5 R7 R30 R32 R36 T1 T4 T6 T31 T33 T36 U1 U36 V1 V2 V34 V36 W1 W2 W34 W36 Y1 Y36 AA1 AA4 AA6 AA31 AA33 AA36 AB1 AB5 AB7 AB30 AB32 AB36 AC1 AC4 AC6 AC31 AC33 AC36 AD1 AD5 AD7 AD30 AD32 AD36 AE1 AE4 AE6 AE31 AE33 AE36 AF1 AF5 AF7 AF30 AF32 AF36 AG1 AG4 AG6 AG8 AG29 AG31 AG33 Pin Name (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) Pin No. AG36 AH1 AH5 AH7 AH9 AH28 AH30 AH32 AH36 AJ1 AJ4 AJ6 AJ8 AJ10 AJ27 AJ29 AJ31 AJ33 AJ36 AK1 AK5 AK7 AK9 AK11 AK13 AK15 AK22 AK24 AK26 AK28 AK30 AK32 AK36 AL1 AL4 AL6 AL8 AL10 AL12 AL14 AL16 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL36 AM1 AM5 AM7 AM9 AM11 AM13 AM15 AM22 AM24 AM26 AM28 AM30 AM32 AM36 AN1 AN4 AN6 AN8 AN10 AN12 AN14 AN16 AN21 Pin Name (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (GND) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) (VDD) Pin No. AN23 AN25 AN27 AN29 AN31 AN33 AN36 AP1 AP2 AP18 AP33 AP36 AR2 AR35 AT3 AT4 AT5 AT6 AT7 AT8 AT9 AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 C4 C19 C35 D18 D19 E18 E19 V3 V4 V5 V32 V33 V35 W3 W4 W5 W32 W33 W35 AM18 AM19 AN18 AN19 AP4 AP19 AP35 Pin Name (TEST1) (TEST1) (TEST2) (TEST2) (TEST3) (TEST3) (TEST4) (TEST4) (TEST5) (TEST5) (TEST6) (TEST6) (TEST7) (TEST7) (TEST8) (TEST8) (TEST9) (TEST9) (TEST10) (TEST10) (TEST11) (TEST11) (TEST12) (TEST12) (TEST13) (TEST13) (TEST14) (TEST14) (TEST15) (TEST15) (TEST16) (TEST16) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) Pin No. W31 Y31 AE29 AF28 AH26 AJ25 AL19 AL20 AL17 AL18 AH11 AJ12 AE8 AF9 W6 Y6 U6 V6 L9 M8 H12 J11 F17 F18 F19 F20 H25 J26 L28 M29 U31 V31 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 C3 C5 C6 C7 C8 C9 C10 C11
REV. A
-49-
AD14160/AD14160L
PIN CONFIGURATIONS (Alphabetical Listing Continued)
Pin Name (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) Pin No. C12 C13 C14 C15 C16 C17 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C34 D2 D3 D5 D7 D9 D11 D13 D15 D17 D20 D22 D24 D26 D28 D30 D32 D34 D35 E2 E3 E4 E6 E8 E10 E12 E14 E16 E17 E20 E21 E23 E25 E27 E29 E31 E33 E34 E35 F2 F3 F5 F7 F9 F11 F13 F15 F22 F24 F26 F28 F30 F32 Pin Name (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) Pin No. F34 F35 G2 G3 G4 G6 G8 G10 G12 G14 G23 G25 G27 G29 G31 G33 G34 G35 H2 H3 H5 H7 H9 H11 H26 H28 H30 H32 H34 H35 J2 J3 J4 J6 J8 J10 J27 J29 J31 J33 J34 J35 K2 K3 K5 K7 K9 K28 K30 K32 K34 K35 L2 L3 L4 L6 L8 L29 L31 L33 L34 L35 M2 M3 M5 M7 M30 M32 M34 M35 N2 N3 Pin Name (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) Pin No. N4 N6 N17 N18 N19 N20 N21 N31 N33 N34 N35 P2 P3 P5 P7 P19 P20 P21 P30 P32 P34 P35 R2 R3 R4 R6 R31 R33 R34 R35 T2 T3 T5 T20 T21 T22 T23 T32 T34 T35 U2 U3 U4 U5 U32 U33 U34 U35 W14 W15 Y2 Y3 Y4 Y5 Y14 Y15 Y32 Y33 Y34 Y35 AA2 AA3 AA5 AA14 AA15 AA32 AA34 AA35 AB2 AB3 AB4 AB6 Pin Name (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) Pin No. AB14 AB15 AB31 AB33 AB34 AB35 AC2 AC3 AC5 AC7 AC30 AC32 AC34 AC35 AD2 AD3 AD4 AD6 AD31 AD33 AD34 AD35 AE2 AE3 AE5 AE7 AE30 AE32 AE34 AE35 AF2 AF3 AF4 AF6 AF8 AF29 AF31 AF33 AF34 AF35 AG2 AG3 AG5 AG7 AG9 AG28 AG30 AG32 AG34 AG35 AH2 AH3 AH4 AH6 AH8 AH10 AH27 AH29 AH31 AH33 AH34 AH35 AJ2 AJ3 AJ5 AJ7 AJ9 AJ11 AJ26 AJ28 AJ30 AJ32 Pin Name (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) Pin No. AJ34 AJ35 AK2 AK3 AK4 AK6 AK8 AK10 AK12 AK14 AK23 AK25 AK27 AK29 AK31 AK33 AK34 AK35 AL2 AL3 AL5 AL7 AL9 AL11 AL13 AL15 AL22 AL24 AL26 AL28 AL30 AL32 AL34 AL35 AM2 AM3 AM4 AM6 AM8 AM10 AM12 AM14 AM16 AM17 AM20 AM21 AM23 AM25 AM27 AM29 AM31 AM33 AM34 AM35 AN2 AN3 AN5 AN7 AN9 AN11 AN13 AN15 AN17 AN20 AN22 AN24 AN26 AN28 AN30 AN32 AN34 AN35 Pin Name (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) (unused) Pin No. AP3 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP34 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34
-50-
REV. A
AD14160/AD14160L
ORDERING GUIDE
Part Number AD14160BB-4* AD14160/AD14160LBB-4* AD14160KB-4 AD14160/AD14160LKB-4
Case Temperature Range -40C to +100C -40C to +100C 0C to +85C 0C to +85C
Instruction Rate 40 MHz 40 MHz 40 MHz 40 MHz
Operating Voltage 5V 3.3 V 5V 3.3 V
NOTES 1. Part numbers marked with an * are shipping as x-grade (preproduction) material at the time of this printing. 2. These parts are packaged in a 452-lead Ceramic Ball Grid Array Package (CBGA). 3. Military and Industrial temperature SMD parts, in the same package are in development.
PACKAGE DIMENSIONS
Dimensions shown in inches and (mm).
452-Lead Ceramic Ball Grid Array (CBGA) (QS-452)
1.862 (47.295) SQ 1.838 (46.685) 1.795 (45.593) SQ 1.785 (45.339)
SOLID COPPER BALL SOLDER COATED 4 PLACES
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
TOP VIEW
PIN A1 INDEX 0.060 (1.524) 0.040 (1.016)
PIN A1 0.030 (0.762) x 45 1 PLACE 0.110 (2.794) 0.090 (2.286)
0.015 (0.381) x 45 3 PLACES 0.170 (4.318) MAX 0.200 (5.08) MAX
BOTTOM VIEW
0.060 (1.524) 0.040 (1.016)
0.033 (0.838) TYP
0.055 (1.397) 0.045 (1.143)
0.024 (0.610) TYP
REV. A
-51-
-52-
C3255-7-1/98
PRINTED IN U.S.A.

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